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   Static Power Dissipation
• There is always static power dissipation due to reverse
biased leakage current between diffusion areas and
substrate.
• Parasitic reverse biased diodes leakage current can be
written as

I = Is [exp(qv/kT) -1]
• It value is 0.1 nA to 0.5 nA at room temperature.
• Static power dissipation is product of current multiply by
supply voltage.
The total power in chip Ps = ∑ In X sup voltage

Lecture-13@IIIT-Allahabad
   Static Power Dissipation
• For CMOS inverter n=2 , Vdd = 5V, I = 0.5 nA

P = 1 nW.

• In NMOS and other inverters there is the direct

path between VDD and Vss thus static power
dissipation is more in these cases
• Static power dissipation for these inverters becomes

The
 
total power in chip P = Pstatic + Idn Vdd

Lecture-13@IIIT-Allahabad
   Short-circuit Power Dissipation
• This power consumption is due to short-circuit current
between Vdd and Vss.

• This depends mainly on fall and rise time.

• If signal takes long time to rise or fall there are the
chances both n and p-transistors are on and current flows.
• N-tr starts conducting after Vin > Vtn
• P-tr Conducts unless Vin = Vdd + Vtp.
• During this period a current starts flowing from min value ,
reaches max and again starts decreasing and finally
  becomes 0.

Lecture-13@IIIT-Allahabad
   Short-circuit Power Dissipation

Lecture-13@IIIT-Allahabad
   Short-circuit Power Dissipation
• Calculate Mean value of the current, Imean
• Power dissipation = Imean X Vdd
To Calculate current consider symmetrical behavior around t2 and i.e. tr
= tf = trf, kn=kp = k and max current in sat.
t2

I mean  2.( 2 / T )  (k / 2)[Vin (t )  Vt ] dt 2

t1

vin(t) = t x Vdd / tr, t1= (Vt x tr)/Vdd, t2 = tr/2

PSC  ( k / 12)[VDD  2Vt ]3 (t rf / t )
total power = Pd + psc + Ps
Lecture-13@IIIT-Allahabad
   Power-Delay product
• Used to measure quality and performance of process.

• This is equal to energy required for a gate to switch from high-to low
or low-to-high.

• Energy required to switch output PDP = Cload Vdd2

• This is equal to average dynamic power dissipation.

• The same energy is dissipated in heat form.

• From design point of view we need minimum PDP.

 

• It can also be defines as product of 2 x Pav x tp

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Lecture-13@IIIT-Allahabad
STATIC TIMING ANALYSIS
 Setup time
:- is defined as the minimum amount of time
BEFORE the clock’s active edge by which
the data must be stable for it to be latched
correctly.
Any violation in this minimum required time
causes incorrect data to be captured and is
known as setup violation.
 Hold time
:- is defined as the minimum amount of time
AFTER the clock’s active edge during
which the data must be stable.
Any violation in this required time causes
incorrect data to be latched and is known as
hold violation
• Clock skew:- the phenomenon in synchronous
circuits in which the clock signal arrives at
different components at different times.
• Slack:- amount of time between event’
actually happens and when it’ must happen
 setup time
• The setup time in a design determines the maximum
frequency at which the chip can run without any timing
failures.
• Factors affecting the setup analysis are the
• clock period Tclk,
• Clock to Q propagation delay of the launch flop
Tck->q,
• negative clock skew Tskew,
• required setup time of the capture flop Tfs and
• combinational logic delay Tcomb between the two
flops being timed.
• The following condition must be satisfied.
• Tfs <= Tclk – Tck->q – Tskew – Tcomb
 Hold Time
• Hold analysis depends on the
• Tck->q,
• combinational logic delay,
• the clock skew and the hold time requirement
Tfh of the capture flop.
• It is independent of the frequency of the
clock.
• The condition below must be satisfied.
• Tck->q + Tskew + Tcomb >= Tfh
• Consider the figure below depicting a flop to
flop path in the same domain with some
combinational logic between them.
• We will now calculate the setup and hold
time slacks in the design based on the given
timing parameters.
• For setup checks in single cycle paths, the
clock edges that are relevant is shown in the
Figure above. The data required time for the
capture flop B to meet setup is
• Data Required time = (Clock Period + Clock
Insertion Delay + Clock Skew - Setup time of
the flop) = 8 + 2 + 0.25 -0.1 = 10.15 ns
• The data arrival time from the launch flop is
• Data Arrival time = (Clock Insertion Delay +
CK->Q Delay of the launch flop +
Combinational logic Delay) = 2 + 0.1 + 5 = 7.1
ns.
• Setup slack is
• Setup Margin = Data Required Time - Data Arrival Time
= 10.15 - 7.10 = 3.05 ns
• Similarly for hold checks assuming the hold time
requirement of the flop B is 100 ps, the data expected
time is
• Data expected time = (Clock Insertion Delay + Clock
skew + Hold time requirement of flop) = 2 + 0.25 +0.1 =
2.35 ns.
• So the hold time slack is  
• Hold Margin = Data Arrival time - Data expected time =
7.10 - 2.35 = 4.85 ns
• Consider the case where the clock to flop B is
inverted (or that the flop is negative edge
trigerred). In this particular case, the relevant
edges for setup/hold are as shown in the
figure below.
• In this scenario, the setup margin considering
all the other parameters to be the same is
• Data Required time = (half_clock_period +
clock insertion delay + Ck->Q delay of flop A -
Setup time required for flop B) = 4 + 2 + 0.25
-0.1 = 6.15 ns
• Since the Data Arrival time remains the same,
there is a setup violation of
• Setup violation = 6.15 ns - 7.10 ns = -1.05 ns
• There is no hold violation since the data
arrival time remains the time but the data
expected time is any time after (Clock skew +
Hold time requirement of flop B)
• Data expected time = 0.25 + 0.1 = 0.35 ns
• Hold Margin = 7.10 - 0.35 = 6.75 ns
 How to solve setup & Hold
violations in the design
1. optimizing/restructuring combination logic between
the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 ->
DFFXx]
3. Tweak launch-flop to have better slew at the clock
pin, this will make CK->Q of launch flop to be fast
there by helping fixing setup violations.
4. Play with skew [ tweak clock network delay, slow-
down clock to capturing flop and fasten the clock to
launch-flop](otherwise called as Useful-skews)
 To solve Hold Violations
1. Adding delay/buffer[as buffer offers lesser
delay, we go for spl Delay cells whose
functionality Y=A, but with more delay]
2. Making the launch flop clock reaching
delayed
3. Also, one can add lockup-latches [in cases
where the hold time requirement is very
huge, basically to avoid data slip]