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DSP Hardware: (Main Source: DSP Handbook-CRC)

This document provides an overview of DSP hardware, including a brief history of major DSP chips and examples of fixed-point and floating-point DSP devices. It discusses the TI TMS320C25 fixed-point DSP chip from the 1980s, which uses a Harvard architecture with separate program and data memory, and its features including a 16x16 bit multiplier and accumulators. The document also describes the TI TMS320C30 floating-point DSP from the 1980s, which can perform floating-point additions and multiplications at up to 33 MFLOPS and supports various floating-point formats. Finally, it mentions some other DSP chips including the SHARC from Analog Devices and Blackfin processors.

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33 views22 pages

DSP Hardware: (Main Source: DSP Handbook-CRC)

This document provides an overview of DSP hardware, including a brief history of major DSP chips and examples of fixed-point and floating-point DSP devices. It discusses the TI TMS320C25 fixed-point DSP chip from the 1980s, which uses a Harvard architecture with separate program and data memory, and its features including a 16x16 bit multiplier and accumulators. The document also describes the TI TMS320C30 floating-point DSP from the 1980s, which can perform floating-point additions and multiplications at up to 33 MFLOPS and supports various floating-point formats. Finally, it mentions some other DSP chips including the SHARC from Analog Devices and Blackfin processors.

Uploaded by

Don John
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DSP Hardware

(main source: DSP Handbook-CRC)

Amit Kumar Mishra


ECE Department, IITG
What this talk will give you?
 Guidelines
 No rules
 Basics for your lab
 BUT no spoon feeding
DSP vs. other hardware
 Mostly realtime
 What is realtime?

 Few fixed number of functions carried out in loop


 Havard architecture
 Should be upgradable
 Two options
 DSP chip
 FPGAs

 Major players in DSP chip: AD, Motorola and TI


 Major players in FPGA: Xilinx and Altera
Little history
 1978: Intel 2920 an "analog signal processor". (no
multiplier)
 1979: AMI (American megatrends incorporated)
S2811 (a microprocessor peripheral)
 1979: Bell Labs Mac 4 Microprocessor (first single
chip DSP)
 1980 NEC (Nippon electric corporation) µPD7720
and AT&T DSP1 (first stand-alone, complete DSP)
 1983: Texas Instruments (TI) TMS32010 (Harvard
architecture: diff. prog. and data memory)
 Motorola 56000 (1980s)
TMS320 devices
 Introduced: 1982 (TMS32010)
 Harvard architecture (separate program and
data memory and hence bus: WHY?)
 Special instruction set (eg LAC, MAC)
 Two major flavors:
 Fixed point (e.g. TMS320C25: 16 bit)
 Floating point (e.g. TMS320C30: 32 bit)
 Many newer avtars are there (VLIW)
 Best resource: User’s manual from vendors
Fixed-Point Devices: TMS320C25
 16 bit
 10MHz : 100ns cycle time
 Mostly single cycle instructions
 Hence 10 MIPS
 Higher MIPS  costlier; vice versa
Main blocks in C’25
 68 pins
 Onchip memory: 4k ROM +
544 RAM
 Memory measured in 16bit
words NOT in bytes
 Can address 64k data and
64k program memory
(HOW?)
 16x16 bit 1-cycle h/w
multiplier
 32 bit accumulators
Architectural features
 All functions are accumulator based
 Several shifters (why?)
 16 i/p and 16 o/p parallel ports
 1 serial port
 133 instruction based assembly language
 Cross-compliers available (problems?)
Von Numan and Havard architecture
 Separate bus
 Need to specify which
memory an address is
pointing
 Instructions like
 TBLR (Table Read)
 TBLW (TableWrite)
 BLKP (Block transfer
from Program
memory).
Memory organisation
 BUS = 16 bit address pins + 16 bit data pins
 PS and DS pin indicate which memory
 RS (reset pin) gives reset signal
 Then starts execution; always at PM location
0
 It should direct to prog. Location
 Microprocessor/Microcontroller mode
(MC/MP): where is prog. Memory 0
 Which one to use?
Multiplier and ALU
 16 bit multiplier
 One factor in T (temp.) register
 Other from memory
 Result in P (product) register (32 bit; WHY?)
 Can also be stored in accumulator
(PAC/APAC/SPAC)
Some other facts
 Follows 2’s compliment representation
 Sign extended
 133 instructions
 Mostly 1 word (sometimes 2 words)
 Routines and interrupts
TMS320C30 Digital Signal
Processor
 32 bit
 Floating point processor
 16.7 MHz
 60ns execution cycle
 16.7 MIPS (1 cycle: 1 floating pt addition and
1 floating pt. multiplication)
 => max. 33 MFLOPS
Architecture
 2k words RAM 4k words
ROM
 64 word program cache
 RAM/ROM can be used
for both prog. and mem
 Hence hybrid
architecture
Floating point capabilities
 Two 32 bit numbers can be multiplied
 40 bit intermediate result
 24 bit integer multiplier  32 bit ACC
 Supports 3 types of floating formats
 Short
 Single-precision
 Extended-precision
 Number
 Exponent (2’s compliment)
 Sign
 Mantissa (2’s compliment)
Floating point formats
Integer formats
Other features
 All instructions are register based
 2 parallel buses
 114 instructions
 Device needs ½ cycle to fetch data from
internal memory
 2 data address buses and 1 data bus
 2 data-fetches per cycle
Bus structure
Other DSPs
 Super Harvard Architecture Single-Chip
Computer (SHARC): Analog Devices (floating-point
and fixed-point DSP)
 Black-fin: 16/32-bit microprocessors with built-
in Digital Signal Processor (AD)
Many thanks

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