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Bus and Memory Transfers

The document discusses bus and memory transfers. It describes how a bus system uses common lines and multiplexers or three-state gates to efficiently transfer data between registers. Multiplexers or buffers allow one register at a time to connect to the common bus lines based on selection lines. Memory transfers involve reading data from memory into a data register using an address from an address register, or writing data from a register into a specified memory location.

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674 views14 pages

Bus and Memory Transfers

The document discusses bus and memory transfers. It describes how a bus system uses common lines and multiplexers or three-state gates to efficiently transfer data between registers. Multiplexers or buffers allow one register at a time to connect to the common bus lines based on selection lines. Memory transfers involve reading data from memory into a data register using an address from an address register, or writing data from a register into a specified memory location.

Uploaded by

Daniel Rizvi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Bus and Memory Transfers

Presented by
Prof. Salwan Tajjour
 Common bus system.
 Bus system for four registers.
 Three-state gates
 Memory Transfer. Contents
2
Common bus system

A digital system compossed of many registers, and paths must be


provided to transfer information from one register to another. The
number of wires connecting all of the registers will be excessive if
separate lines are used between each register and all other registers in
the system.
3 2 1 0
R1

3 2 1 0 3 2 1 0 R3
R2
• A bus structure, on the other hand, is more efficient for transferring
information between registers in a multi-register configuration
system.

• A bus consists of a set of common lines, one for each bit of register,
through which binary information is transferred one at a time. Control
signals determine which register is selected by the bus during a
particular register transfer.
Bus system for four registers
• The two selection lines S1 and S2 are connected to the
selection inputs of all four multiplexers. The selection
lines choose the four bits of one register and transfer them
into the four-line common bus.

• When both of the select lines are at low logic, i.e. S1S0 =
00, the 0 data inputs of all four multiplexers are selected
and applied to the outputs that forms the bus. This, in
turn, causes the bus lines to receive the content of register
A since the outputs of this register are connected to the 0
data inputs of the multiplexers.

• Similarly, when S1S0 = 01, register B is selected, and the


bus lines will receive the content provided by register B.

• The following function table shows the register that is


selected by the bus for each of the four possible binary
values of the Selection lines.
The number of multiplexers needed to construct the
bus is equal to the number of bits in each register.
The size of each multiplexer must be 'k * 1' since it
multiplexes 'k' data lines. For instance, a common
Note bus for eight registers of 16 bits each requires 16
multiplexers, one for each line in the bus. Each
multiplexer must have eight data input lines and
three selection lines to multiplex one significant bit
in the eight registers.
• A bus system can also be constructed using
three-state gates instead of multiplexers.

• The three state gates can be considered as a


digital circuit that has three gates, two of
which are signals equivalent to logic 1 and
0 as in a conventional gate. However, the
third gate exhibits a high-impedance state.
Three-state
gates • The most commonly used three state gates
in case of the bus system is a buffer gate.
• The outputs generated by the four buffers
are connected to form a single bus line.
• Only one buffer can be in active state at a
given point of time.
• The control inputs to the buffers
determine which of the four normal
inputs will communicate with the bus
line.
• A 2 * 4 decoder ensures that no more than
one control input is active at any given
point of time.
Memory Transfer

• The transfer of information from a memory unit to the user end is


called a Read operation.
• The transfer of new information to be stored in the memory is called
a Write operation.
• A memory word is designated by the letter M.
• We must specify the address of memory word while writing the
memory transfer operations.
• The address register is designated by AR and the data register by DR.
• Thus, a read operation can be stated as:
Read: DR ← M [AR]
• The Read statement causes a transfer of information into the data
register (DR) from the memory word (M) selected by the address
register (AR).
• And the corresponding write operation
can be stated as:
Write: M [AR] ← R1
• The Write statement causes a transfer
of information from register R1 into
the memory word (M) selected by
address register (AR).
23

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