ELECTRICAL INSTRUMENTATION

1
•Digital signal processing is more accurate than analogue
techniques. However
(i)analogue processing is the faster of the two alternatives
(ii)digital processing equipment is more expensive
(iii)Also accuracy is reduced with measurements coming from
analogue sensors and transducers, because an analogue-to-
digital conversion stage is necessary before the digital
processing can be applied, thereby introducing conversion
errors

•Digital signal processing elements in a measurement system

can exist as separate units but are usually part of an intelligent
instrument
•The form that signal processing takes depends on the
software program executed by the processor of the digital
computer
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•Digitalcomputers require signals to be in digital form whereas
most instrumentation transducers have an output signal in
analogue form
• Analogue-to-digital (A/D) conversion is therefore required at the
interface between analogue transducers and the digital computer,
and digital-to-analogue (D/A) conversion is often required at a later
stage to convert the processed signals back into analogue form

Sampling Theorem
•Process of A/D conversion consists of sampling the analogue
signal at regular intervals of time
• Each sample of the analogue voltage is then converted into an
equivalent digital value
•This conversion takes a certain finite time, during which the
analogue signal can be changing in value
•The next sample of the analogue signal cannot be taken until
conversion of the last sample to digital form is completed
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 •A continuous analogue signal is thus represented in digital format
as a sequence of samples whose pattern only approximately
follows the shape of the original signal
• This pattern of samples taken at successive, equal intervals of
time is known as a discrete signal
•Process of conversion between a continuous analogue signal and
a discrete digital one is illustrated below for a sine wave:
•Raw analogue signal frequency
(fraw) ≈ 0.75 cycles per second
•At sampling rate of 11
samples/sec (dotted line), the
sample reconstruction matches
the original analogue signal very
well
•For sampling rate very much less
than fraw e.g.1 sample per second,
only the samples marked ‘X’ would
•. Fitting a line through these ‘X’s incorrectly estimates a signal whose
be obtained 4
frequency is ≈ 0.25 cycles per second
•This phenomenon whereby the process of sampling transmutes a
high-frequency signal into a lower frequency one is called aliasing
•To avoid aliasing, theoretically the sampling rate should be at least
twice the highest frequency in the analogue signal sampled (Nyquist-
Shannon sampling theorem)

•Inpractice, sampling rates of between 5 and 10 times the highest

frequency signal are normally chosen so that the discrete sampled
signal is a close approximation to the original analogue signal in
amplitude and frequency

•Problems can arise in sampling when the raw analogue signal is

corrupted by high frequency noise of unknown characteristics
•If a sampling interval such as a 10-times multiple of the frequency of
the measurement component in the raw signal is chosen, aliasing can
sometimes transmute high-frequency noise components into the
same frequency range as the measurement component in the signal,
thus giving erroneous results. Prior analogue signal conditioning in
the form of a low-pass filter must then be carried out before digital5
processing
Quantisation
•Quantisation describes the procedure whereby the
continuous analogue signal is converted into a number of
discrete levels
•At any particular value of the analogue signal, the digital
representation is either the discrete level immediately above
this value or the discrete level immediately below this value
•If the difference between two successive discrete levels is
represented by the parameter Q, then the maximum error in
each digital sample of the raw analogue signal is Q/2
•This error is known as the quantization error and is
proportional to the resolution of the analogue-to-digital
converter (ADC), i.e. to the number of bits used to represent
the samples in digital form
 Sample and Hold circuit
•Is normally an essential element at the interface between an
analogue sensor or transducer and an ADC
•It holds the input signal at a constant level whilst the A/D conversion
process is taking place
• This prevents the conversion errors that would probably result if
variations in the measured signal were allowed to pass through to the
converter
•The input signal is applied
to the circuit for a very short
time duration with switch
S1 closed and S2 open

•Then S1 is opened and the

signal level is held until,
Op-amp connected when the next sample is
as ’sample and required, the circuit is reset
hold’ circuit by closing S2
 Analog-to-Digital Conversion
•An analogue-to-digital converter (ADC) takes an analogue input
voltage and produces a digital output code that represents the
analog input

•A/Dconversion process is generally more complex and time-

consuming than the D/A conversion process
•Several types of ADCs utilize a digital-to-analogue converter
(DAC) as part of their circuitry

•Important factors in the design of an ADC are

the speed of conversion
the number of digital bits used to represent the analogue
signal level

•Several types of analogue-to-digital converter exist. These

differ in the technique used to effect signal conversion, in
operational speed, and in cost
Counter ADC
•At the start of each conversion cycle, the counter is set to zero
•The digital counter value is converted to an analogue signal by a
DAC, and a comparator then compares this analogue counter value
with the unknown analogue signal
•The comparator output forms one of the inputs to an AND logic
gate, the other input being a sequence of clock pulses. The
comparator acts as a switch that can turn on and off the passage of
pulses from the clock through the AND gate
•The output of the AND gate is connected to the input of the digital
counter
•Following the initial reset of the counter, clock pulses are applied
continuously to the counter through the AND gate, and the
analogue signal at the DAC output gradually increases in
magnitude
•At some point in time, this analogue signal becomes equal in
magnitude to (or slightly greater than) the unknown signal at the
input to the comparator. The output of the comparator then changes
state, closing the AND gate and stopping further counter increments
•At this point, the value held in the counter is a digital representation
 Dual slope ADC
•The dual-slope converter has one of the slowest conversion
times (typically 10 to100 ms) but has the advantage of relatively
low cost because it does not require precision components such
as a DAC or a Voltage Controlled Oscillator (VCO)

Basic Operation
•Involves the linear charging and discharging of a capacitor
using constant currents
•First, the capacitor is charged up for a fixed time interval from a
constant current derived from the analog input voltage, Vi. Thus
at the end of this fixed charging interval, the capacitor voltage
will be proportional to Vi
•At that point, the capacitor is linearly discharged from a constant
current derived from a precise reference voltage, Vref
• When the capacitor voltage reaches 0, the linear discharging is
terminated
•During the discharge interval, a digital reference frequency is
fed to a counter and counted. The duration of the discharge
interval will be proportional to the initial capacitor voltage
•At the end of the discharge interval, the counter will hold a
count proportional to the initial capacitor voltage, which is
proportional to Vi

•In
addition to low cost, another advantage of the dual-slope
ADC is its low sensitivity to noise and to variations in its
component values caused by temperature changes
•
 Voltage-to-Frequency ADC
•The voltage-to-frequency ADC is simpler than other ADCs
because it does not use a DAC
•Instead it uses a linear voltage-controlled oscillator (VCO) that
produces an output frequency proportional to its input voltage
•The analog voltage to be converted is applied to the VCO to
generate an output frequency
•This frequency is fed to a counter to be counted for a fixed time
interval. The final count is proportional to the value of the analog
voltage

•E.g. if the VCO generates a frequency of 10 kHz for each volt of

input and if the analog input voltage is 4.54 V, then the VCO output
will be a 45.4kHz signal that clocks a counter for, say, 10 ms. After
the 10-ms counting interval the counter will hold the count of 454,
which is the digital representation of 4.54 V
•Though a simple method of conversion, it is difficult to achieve a
high degree of accuracy because of the difficulty in designing
VCOs with accuracies of better than 0.1 %

•Isused in noisy industrial environments where small analog

signals must be transmitted from transducer circuits to a control
computer. The small analog signals can be drastically affected
by noise if they are directly transmitted to the control computer

• A better approach is to feed the analog signal to a VCO, which

generates a digital signal whose output frequency changes
according to the analog input. This digital signal is transmitted to
the computer and will be much less affected by noise

FOR OWN STUDY

Read about the Successive-Approximation Converter
 Digital-to-Analogue Conversion
•Isthe process of taking a value represented in digital code and
converting it to a voltage or current that is proportional to the
digital value

•It
is much simpler to achieve D/A conversion than A/D
conversion and cost of hardware is also considerably less

•Itis required when the output of an intelligent instrument needs

to presented on a display device that operates in an analogue
manner

•Twotypes of Digital-to-Analogue converter (DAC) include the

Weighted Resistor DAC and the R/2R ladder DAC
 Resolution (Step Size)
• Is defined as the smallest change that can occur in the analog
output as a result of a change in the digital input
• It is also referred to as the step size, as it’s the amount that VOUT
will change as the digital input value is changed from step to step

Output waveforms of a DAC as inputs

are provided by a binary counter
 Afs
Resolution  n
2 -1

where Afs is the analog full-scale output and n is the number of bits

• Note: The staircase has 16 levels corresponding to the 16 input

states but there are only 15 steps or jumps between the 0-V level
and full-scale

In general, for an N-bit DAC, the number of different levels will

be 2N and the number of steps will be 2N – 1
 Percentage Resolution
• Although resolution can be expressed as the amount of voltage or
current per step, it is also useful to express it as a percentage of
the full-scale output:
step size
% resolution  x100%
full scale

• Alternatively
1 1
% resolution  x100%  N x100%
total number of steps 2 -1

for an N-bit input code

The significance of resolution:
• A DAC cannot produce a continuous range of output values so,
strictly speaking, its output is not truly analog
• The DAC's resolution (number of bits) determines how many
possible voltage values can be generated

Say for instance a DAC’s expected analog output voltage is

between 0 and 10 V. If a six-bit DAC is used, there will be 63
possible steps of 0.159 V between 0 and 10 V. When an eight-bit
DAC is used, there will be 255 possible steps of 0.039 V between 0
and 10 V

• The greater the number of bits, the finer the resolution (the smaller
the step size)

• The resolution limits how close the DAC output can come to a
given analog value
• Generally, the cost of DACs increases with the number of bits so a
system designer will use only as many bits as necessary
a) Weighted Resistor DAC
•Inputs A, B, C, D are
binary inputs with values of
either 0 or 5 V
•The op-amp, a summing
amplifier, produces the
weighted sum of these
input voltages.
•The summing amplifier
multiplies each input
voltage by the ratio of the
feedback resistor RF to the
corresponding input
Binary- weighted resistor DAC resistor RIN

•RF = 1 kΩ. The D input has RIN = 1 kΩ, so the voltage at D is passed
with no attenuation. The C input has RIN = 2 kΩ so it is attenuated by
1/2. Similarly, the B input is attenuated by 1/4, and the A input by 1/8
• The amplifier output can thus be expressed as

VOUT   VD  1 VC  1 VB  1 VA
2 4 8

The negative sign is present because the summing amplifier is
a polarity-inverting amplifier

• Note: The resistors are binarily weighted, i.e. starting with the
MSB resistor, the resistor values increase by a factor of 2
 b) R/2R Ladder DAC
•While the use of binary-weighted resistors to produce the proper
weighting of each bit works in theory, it has some practical limitations
• The biggest problem is the large difference in resistor values
between the LSB and the MSB, especially in high-resolution DACs
(i.e., many bits)
• E.g. if the MSB resistor is 1 kΩ in a 12-bit DAC, the LSB resistor will
be over 2 MΩ
•With current IC fabrication technology, it is very difficult to produce
resistance values over a wide resistance range that maintain an
accurate ratio especially with variations in temperature

•Thus a circuit that uses resistances that are fairly close in value is
preferable
•The R/2R ladder network, where the resistance values span a range
of only 2 to 1, is one of the most widely used DAC circuits that
satisfies this requirement
•It consists of a resistor-ladder network on the input to an operational
amplifier
 8-bit R/2R
ladder DAC

The analogue output voltage from the amplifier is given by:

•V0 …. V7 are set at either the reference voltage level Vref or at
zero volts according to whether an associated switch is open or
closed
•Each switch is controlled by the logic level of one of the bits 0–
7 of the 8 bit binary signal being converted
• A particular switch is open if the relevant binary bit has a value
of 0 and closed if the value is 1

•Consider for example a digital signal with binary value of

11010100. The values of V7 ….. V0 are therefore:
V7 = V6 = V4 = V2 = Vref ; V5 = V3 = V1 = V0 =0

•The analogue output from the converter is then given by:

 DAC Specifications
 Resolution

 Accuracy
• Two ways of specifying accuracy are:

(i) Full-scale error: Is the maximum deviation of the DAC's output

from its expected (ideal) value, expressed as a percentage of full
scale.
E.g. If a DAC has an accuracy of ±0.01% F.S. and a full scale
output of 9.375 V, this percentage converts to

±0.01% X 9.375 V = ±0.9375 mV

(ii) Linearity error : Is the maximum deviation in step size from the
ideal step size
• Also normally expressed as a percentage of the converter's full-
scale output (% F.S.)
 Offset Error
• Ideally, a DAC’s output will be zero volts when the binary
input is all 0s
• In practice however, there will be a very small output voltage
for this situation, called the offset error
• This offset error, if uncorrected, will be added to the
expected DAC output for all input cases
• Offset error can be negative as well as positive
Ideal and actual DAC output for a four-bit DAC with an offset error of
+2 mV and a perfect step size of 100 mV
 Settling Time
• Specifies the operating speed of a DAC
• Settling time is the time required for the DAC output to go from
zero to full scale as the binary input is changed from all 0s to all
1s
• It is measured as the time for the DAC output to settle within ± 1/2
step size (resolution) of its final value

 Monotonicity
• A DAC is monotonic if its output increases as the binary input is
incremented from one value to the next
• The staircase output will have no downward steps as the binary
input is incremented from zero to full scale