S.R.K.R.

ENGINEERING COLLEGE (AUTONOMOUS)

CHINA AMIRAM, BHIMAVARAM, A.P., INDIA, PIN-534204.

A High-Speed Low-Cost Self-Checking Carry Select Adder with Multiple Fault

Detection utilizing optimized Add-One Circuit and Multiplexer-Based Logic

SRI. T. V. SYAMALA RAJU (M.TECH)

K . R AV I K I R A N (18B91A0485)
K . D E E P I K A S O W M YA ( 1 8 B9 1 A 0 4 B4 )
K. KARUNAKAR ( 1 8 B9 1 A 0 4 8 7 )
K. HARI KRISHNA ( 1 8 B9 1 A 0 4 7 8 )
CONTENTS
1. Abstract
2. Introduction
3. Background
(1) Carry select adder
(2) Carry select adder with the SQRT grouping
(3) Principle of Self-checking FA
(4) Self-checking FA Circuit Diagram
(5) Modified self-checking CSeA design
(6) Modified 2-bit self-checking CSeA Circuit Diagram
4. References
ABSTRACT
Employing cost-efficient, high speed and fault tolerant processing units is an essential goal in the


design of current processors.

The main aim is to design the self-checking Carry Select Adder (CSeA) with Multiple-Fault Detection


capability by improving delay, required area and power consumption.

The CSeA as one of the fastest adders is designed using the concept of self-checking full adder and


the conventional square-root (SQRT) grouping to optimize the overall delay of the adder.
An m-bit logic-optimized self-checking CSeA is designed in which at most ‘m’ concurrent faults can


be detected.
The proposed CSeA reaches in average 20% power reduction and (30-34)% speed improvement in


different sizes compared to the best existing design.

INTRODUTION
Nowadays, the VLSI systems are more encountering both transient and permanent faults
because of the factors such as shrinking power supply voltages and diminishing transistor
feature sizes.
Therefore, the VLSI-based circuits especially the processors should be reconsidered to be
reinforced against different types and numbers of faults in the form of fault detection.
Regarding the fault detection property, the concept of self-checking is used which includes
fault-secure and self-testing characteristics, and such a system is called totally self-checking.
A circuit is said fault-secure if it remains unaffected by a fault or it indicates a fault as soon as it
occurs.
The square-root (SQRT) carry select adder (CSeA) as one of the fastest adders having lower
delay is considered for this project.
INTRODUTION

In the basic SQRT scheme, to optimize the worst-case delay, the different-size groups normally
including two ripple carry adder (RCA) sections in parallel are utilized.
To attain multiple fault detection capability, the fault-detection is independently performed in
each bit of the CSeA based on the concept of a self-checking full adder (FA).
In addition, to reduce area and delay, a fast and small multiplexer (MUX) is used for the
selection of proper sum and carry in each group.
 BACKGROUND
Carry select adder:
In the basic single-stage or single-group CSeA
two units exist, the sum and carry generation
unit, and the sum and carry selection unit. The
former normally consists of two RCAs, and the
latter is a simple multiplexer with an appropriate
size. One of the RCAs performs the add
operation with the input carry assumed equal to
zero and the other RCA operates with the input
carry assumed equal to one. After determination
of the real incoming carry, the proper sum and
output carry will be selected in the second unit,
and this way, the speed improves because the
parallel RCAs prepare all potential results before
the arrival of the input carry.
 BACKGROUND
Carry select adder with the SQRT
grouping:
If the same-size groups are used, the best
size for lowering the delay is the square
root of the adder size. However, if
different-size groups are allowed, the
increasing size of single-stage CSeAs in the
SQRT grouping exploits the maximum
concurrency in the carry propagation path
which leads to lower delay compared to
the same-size groups. In the SQRT
grouping, the adder delay approximately
increases with the square root of adder
size growth.
BACKGROUND
Concept of SQRT grouping:
For the 8-bit multi-stage CSeA the best SQRT grouping includes a 2-bit RCA, and two groups
with the sizes of 2 and 4 bits, respectively.
The 16-bit SQRT CSeA consists of a 2-bit RCA, and the groups with the sizes of 2, 3, 4 and 5 bits,
respectively.
For the 32-bit SQRT CSeA after the first 2-bit RCA, the groups with the sizes of 2, 3, 4, 6, 7 and 8
bits lead to the minimum delay.
 And for the 64-bit SQRT CSeA after the first 2-bit RCA, the groups with the sizes of 2, 3, 4, 6, 7,
8, 9, 11 and 12 bits are used
BACKGROUND
Principle of Self-checking FA:
When all three inputs of FA including input operands A and B, and input carry
Cin are equal, then, the output sum (Sum) and output carry (Cout) will be equal.
In addition, the output sum and carry bits will be complemented if one of the
three inputs is different. This property can be used for designing a self-checking
FA with the cost of the equivalence tester (Eqt) and error detection logic.
 BACKGROUND
Principle of Self-checking FA (cont’d):
In the following, Eqs. (1) and (2) describe the operation of FA, and Eqs. (3) and (4)
describe the operation of equivalence tester and error detection logic, respectively,
required for the self-checking FA.
Sum = A⨁B⨁Cin (1)
Cout= A.B +Cin.(A+B) (2)
Eqt =(A.B.Cin +A’.B’.Cin’)’ (3)
Error= Sum⨀Cout⨀Eqt (4)
BACKGROUND
Principle of Self-checking FA (cont’d):
Based on Eq. (3), the equivalence tester checks the inputs, and Eqt will be '0' if the
equivalence is verified; otherwise, it will be '1'. Then, in Eq. (4) the first XNOR operation
checks whether Sum and Cout are equal or not which produces '1' or '0', respectively.
Finally, Eq. (4) sets Error to '1' with the second XNOR operation if the values of Eqt and
the output of the first XNOR operation are equal which means a single fault has been
detected. Otherwise, the FA is fault-free or more than a single fault exist.
In order to detect all single faults which is required for the self-checking property, the
outputs of FA i.e. Sum and Cout should not have any shared logic as shown in Fig. 2.
This way, any fault occurring inside the FA will effect on a single component related to
either Sum or Cout, thus, will be detected by comparison according to Eq. (4).
BACKGROUND
Self-checking FA Circuit Diagram:
SELF-CHECKING CSeA
ARCHITECTURES
1. BEC based self-checking CSeA design:
The basic m-bit single-stage CSeA includes two m-bit RCAs, and an (m+1)-bit
multiplexer to select the proper m-bit sum and 1-bit output carry. Naturally, the
self-checking property is attained with the cost of some area, power and delay
overheads. Thus, to obtain a low-overhead self-checking CSeA is modified. In
this CSeA, the second RCA is replaced by the BEC logic which includes only one
XOR gate and one AND gate in all bit positions except the first one which
requires only a NOT gate. This way, the obtained self-checking single-stage CSeA
will have lower area and power compared to previous self-checking CSeA
designs.
SELF-CHECKING CSeA
ARCHITECTURES
m-bit single-stage BEC-CSeA Circuit Design:
SELF-CHECKING CSeA
ARCHITECTURES
2. CSeA with Fast Add-one and Multiplexing(FAM) Circuit Design:
FAM CSeA is proposed in which the add-one operation is performed combined
with the MUX operation.
This combination results an efficient CSLA architecture with respect to delay,
area and power consumption.
To achieve more speed, two fast Self-Checking Full Adder structures are
incorporated inside the single RCA of the FAM CSeA design.
The first FA is a low-area MUX-based circuit from Ref. [2] and the second is a
high-speed FA based on skip logic. This logic that includes one OR and one AND
gate is similar to the skip logic in the carry skip adder.
SELF-CHECKING CSeA
ARCHITECTURES
2.1. CSeA-FAM Circuit Design:
SELF-CHECKING CSeA
ARCHITECTURES
2.2. Fast Full-Adder Designs:
MUX-Based FA Skip logic based FA
SELF-CHECKING CSeA
ARCHITECTURES
CGS(Carry Generation and Selection) based CSeA Design:
Below diagram illustrates the CGS based self-checking single-stage CSeA based
on Ref. [1] .In the above figure, the upper block generates half-sum in addition
to Propagate and Generate signals where the latter is used as the half-carry, as
well. And remaining blocks will be involved in error detection. Two FCG blocks as
the full-carry generation blocks produce two carry vectors in parallel.
One of these carry vectors will be selected by the multiplexer which includes m
2-to-1 MUXs.
In this design the redundant logic is removed which reduces the area and
power consumption.
*BEC-CSeA Results:
Specifications 16-Bit 32-Bit 64-Bit
LUT 32 69 145
POWER 0.196W 0.455W 0.953W
SETUP DELAY 5.847ns 11.735ns 23.118ns
HOLD DELAY 1.906ns 2.767ns 2.834ns
ADP 187.104 809.715 3352.11
EDP 1.146012 5.339425 22.031454

*CGS-CSeA Results:
Specifications 16-Bit 32-Bit 64-Bit
LUT 29 70 148
POWER 0.19W 0.470W 1.003W
SETUP DELAY 9.659ns 12.816ns 17.607ns
HOLD DELAY 2.407ns 2.885ns 3.062ns
ADP 280.111 897.11 2605.836
EDP 1.835 6.0235 17.6598
*FAM Results:
Specifications 16-Bit 32-Bit 64-Bit
LUT 30 67 133
POWER 0.195W 0.428W 0.867W
SETUP DELAY 9.058ns 11.962ns 15.988ns
HOLD DELAY 2.378ns 2.681ns 2.730ns
ADP 271.74 801.454 2126.404
EDP 1.76631 5.119736 13.861596

*MFAM Results:
Specifications 16-Bit 32-Bit 64-Bit
LUT 30 69 134
POWER 0.186W 0.433W 0.877W
SETUP DELAY 8.553ns 12.583ns 15.985ns
HOLD DELAY 2.392ns 2.634ns 2.775ns
ADP 259.59 868.227 2141.99
EDP 1.590858 5.448439 14.018845
REFERENCES
 [1] A low-cost high-speed self-checking carry select adder with multiple-fault detection
Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi
[2] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha, J. Chung, A novel multiplexer-based low-power full
adder, IEEE Transactions on Circuits and Systems II: Express Briefs 51 (7) (2004) 345–348.
[3] M. A. Akbar, J. Lee, Self-repairing adder using fault localization, Microelectronics Reliability,
vol. 54, no. 6-7, pp. 1443–1451, Jun.-Jul. 2014.