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A Pipelined Datapath: Resisters Are Used To Save Data Between Stages

The document describes the implementation of a pipelined datapath for a processor. It discusses how registers are used to store data between pipeline stages and how control signals must also be passed through the pipeline. It further describes how data hazards can occur due to dependencies between instructions and how techniques like forwarding, stalling, and bubbling can resolve such hazards in the pipeline. A hazard detection unit is used to detect hazards and enable the appropriate handling technique.

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JohnDaGRT
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100 views14 pages

A Pipelined Datapath: Resisters Are Used To Save Data Between Stages

The document describes the implementation of a pipelined datapath for a processor. It discusses how registers are used to store data between pipeline stages and how control signals must also be passed through the pipeline. It further describes how data hazards can occur due to dependencies between instructions and how techniques like forwarding, stalling, and bubbling can resolve such hazards in the pipeline. A hazard detection unit is used to detect hazards and enable the appropriate handling technique.

Uploaded by

JohnDaGRT
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 14

A Pipelined Datapath

Resisters are used to save data between stages.


0 M u x 1

IF/ID Add 4

ID/EX

EX/MEM

MEM/WB

Add Add result Shift left 2

PC

Address Instruction memory

Instruction

Read register 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

0 M u x 1

Zero ALU ALU result

Address Data memory Write data

Read data

1 M u x 0

16

Sign extend

32

Computer

Architecture - A Pipelined Datapath

1/14

Corrected Datapath
The Write Register in the IF/ID register is from the wrong instruction. The Write Register is passed through the pipeline and forwarded to the Register File (RF) from the MEM/WB register.
0 M u x 1 IF/ID ID/EX EX/MEM MEM/WB Add 4 Add Add result Shift left 2 PC Address Instruction memory

Instruction

Read register 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

0 M u x 1

Zero ALU ALU result

Address Data memory Write data

Read data

1 M u x 0

16

Sign extend

32

Computer

Architecture - A Pipelined Datapath

2/14

1 Write data 16 Sign extend 32

Instructions in the Pipeline (Clock 2)


Clock 1

sub $11,$2,$3
sub $11, $2, $3 Instruction fetch
0 M u x 1

lw $10,20($1)
lw $10, 20($1) Instruction decode

IF/ID

ID/EX

EX/MEM

MEM/WB

Add 4 Shift left 2 Add Add result

PC

Address Instruction memory

Instruction

Read register 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

0 M u x 1

Zero ALU ALU result

Address Data memory Write data

Read data

1 M u x 0

16

Sign extend

32

Clock 2

Computer

Architecture - A Pipelined Datapath

3/14

16

Sign extend

32

Instructions in the Pipeline (Clock 4)


Clock 3

sub $11,$2,$3
0 M u x 1

lw $10,20($1)
lw $10, 20($1) Memory

sub $11, $2, $3 Execution

IF/ID

ID/EX

EX/MEM

MEM/WB

Add 4 Shift left 2 Add Add result

PC

Address Instruction memory

Instruction

Read register 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

0 M u x 1

Zero ALU ALU result

Address Data memory Write data

Read data

1 M u x 0

16

Sign extend

32

Clock 4

Computer

Architecture - A Pipelined Datapath

4/14

Instructions in the Pipeline (Clock 5)


sub $11,$2,$3 lw $10,20($1)
0 M u x 1

sub $11, $2, $3 Memory

lw $10, 20($1) Write back

IF/ID

ID/EX

EX/MEM

MEM/WB

Add 4 Shift left 2 Add Add result

PC

Address Instruction memory

Instruction

Read register 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

0 M u x 1

Zero ALU ALU result

Address Data memory Write data

Read data

1 M u x 0

16

Sign extend

32

Clock 5

Computer
0

Architecture - A Pipelined Datapath

5/14 sub $11, $2, $3

Pipelined Control
Problem: Control lines are defined in the IF stage. Example: In the WB stage MemtoReg and RegWrite are opcode dependent. Solution: Pass the control lines through the pipeline.
WB Instruction Control M EX WB M WB

IF/ID

ID/EX

EX/MEM

MEM/WB

Computer

Architecture - A Pipelined Datapath

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Pipeline Datapath with Control


PCSrc 0 M u x 1 Control ID/EX WB M EX EX/MEM WB M MEM/WB WB

IF/ID Add 4

RegWrite

Add Add result

ALUSrc

PC

Address Instruction memory

Read data 1 Read register 2 Registers Read Write data 2 register Write data

0 M u x 1

Zero ALU ALU result

Address Data memory Write data

Read data

Instruction 16 [15 0]

Sign extend

32

ALU control

MemRead

Instruction [20 16]

Instruction [15 11]

0 M u x 1 RegDst

ALUOp

Computer

Architecture - A Pipelined Datapath

MemtoReg
1 M u x 0

Instruction

Read register 1

MemWrite

Shift left 2

Branch

Data Dependencies
Backward lines cause data hazards:
Time (in clock cycles) CC 1 Value of register $2: 10 Program execution order (in instructions) CC 2 10 CC 3 10 CC 4 10 CC 5 10/ 20 CC 6 20 CC 7 20 CC 8 20 CC 9 20

sub $2,$1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2)

sub $2, $1, $3

IM

Reg

DM

Reg

and $12, $2, $5

IM

Reg

DM

Reg

or $13, $6, $2

IM

Reg

DM

Reg

add $14, $2, $2

IM

Reg

DM

Reg

sw $15, 100($2)

IM

Reg

DM

Reg

Computer

Architecture - A Pipelined Datapath

8/14

2 Easy Solutions
The RF is written into in the 1st half of the cycle and read from in the 2nd half of the cycle. Thus the data written is the data read. The add instruction isnt a hazard. sub $2,$1,$3 Disallow data hazards by nop adding an nop instruction called and $12,$2,$5 nop (no operation). Now there arent any data hazards.

or $13,$6,$2 add $14,$2,$2 sw $15,100($2)

Computer

Architecture - A Pipelined Datapath

9/14

Detecting And Forwarding


Easy. Each pipeline register contains the Rs, Rt, and Rd of the current instruction. If one of the next equalities is true there is a hazard:
EX/MEM.Rd == ID/EX.Rs EX/MEM.Rd == ID/EX.Rt MEM/WB.Rd == ID/EX.Rs MEM/WB.Rd == ID/EX.Rs

A unit called the Forwarding Unit decides if there is a hazard and solves it by using forwarding. The values are directed from the EX/MEM and MEM/WB registers to the ALU.
Computer Architecture - A Pipelined Datapath
10/14

The Forwarding Unit


a. No forwarding ID/EX EX/MEM MEM/WB

M u x Registers ForwardA M u x ALU Data memory

M u x

Rs Rt Rt Rd

ForwardB M u x Forwarding unit

EX/MEM.RegisterRd MEM/WB.RegisterRd

b. With forwarding

Computer

Architecture - A Pipelined Datapath

11/14

Data Hazards and Stalls


Sometimes Forwarding doesnt work (load-use data hazard):
Time (in clock cycles) Program CC 1 execution order (in instructions) CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9

lw $2,20($1) and $4,$2,$5 or $8,$2,$6

lw $2, 20($1)

IM

Reg

DM

Reg

and $4, $2, $5

IM

Reg

DM

Reg

or $8, $2, $6

IM

Reg

DM

Reg

add $9,$4,$2
slt $1,$6,$7

add $9, $4, $2

IM

Reg

DM

Reg

slt $1, $6, $7

IM

Reg

DM

Reg

Computer

Architecture - A Pipelined Datapath

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Inserting a Bubble
The EX,MEM, and WB control fields of the ID/EX register are set to 0. The PC and IF/ID register arent updated. This causes the and & or instructions to repeat cycle 3 during cycle 4.
Program Time (in clock cycles) execution CC 1 CC 2 order (in instructions) lw $2, 20($1) IM Reg CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 CC 10 DM Reg

and $4, $2, $5

IM

Reg

Reg

DM

Reg

or $8, $2, $6

IM

IM

Reg

DM

Reg

bubble
add $9, $4, $2 IM Reg DM Reg

slt $1, $6, $7

IM

Reg

DM

Reg

Computer

Architecture - A Pipelined Datapath

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Hazard Detection Unit


Hazard detection unit
IF/IDWrite

ID/EX.MemRead ID/EX WB M u x EX/MEM WB M

Control 0

M EX

MEM/WB WB

IF/ID

PCWrite

Instruction

M u x Registers ALU M u x Data memory

PC

Instruction memory

M u x

The hardware doesnt depend on the compiler to detect and eliminate data hazards. A smart compiler will help in order to achieve better performance.
IF/ID.RegisterRs IF/ID.RegisterRt IF/ID.RegisterRt Rt IF/ID.RegisterRd Rd Rs Rt M u x EX/MEM.RegisterRd

Computer

Architecture - A Pipelined Datapath MEM/WB.RegisterRd

ID/EX.RegisterRt

Forwarding unit

14/14

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