Chapter 2.

Machine
Instructions and
Programs
Objectives
 Machine instructions and program execution,
including branching and subroutine call and return
operations.
 Number representation and addition/subtraction in
the 2’s-complement system.
 Addressing modes for accessing register and
memory operands.
 Assembly language for representing machine
instructions, data, and programs.
 Program-controlled Input/Output operations.
Memory Locations,
Addresses, and
Operations
Memory is organized as a large array of bytes or
words

Word is a group of n-bits, ‘n’ is called word length.

Memory is represented as a collection of words.

The word length range from 16 to 64 bits.

Accessing the memory requires address for each

location.
So, use numbers from 0 to 2K -1 to address the
successive memory locations. (K address bits)i.e
memory can have up to . 2K memory locations.
Memory Location, Addresses
n bits
first word
 Memory consists
second word
of many millions of
storage cells,
each of which can •
store 1 bit. •
•
 Data is usually i th word
accessed in n-bit
groups. n is called
word length. •
•
•
last word

Figure 2.5. Memory words.

Memory Location, Addresses,
and Operation
 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location, Addresses,
and Operation
 To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location
are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240
Byte Addressability
 It is impractical to assign distinct addresses
to individual bit locations in the memory.
 The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory – byte-
addressable memory.
 Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…
Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •
k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing.

 Address ordering of bytes
 Word alignment
 Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….
 32-bit word: word addresses: 0, 4, 8,….
 64-bit word: word addresses: 0, 8,16,….
 Access numbers, characters, and character
strings
Memory Operation
 Both program instructions and data are stored in
memory.
 To execution an instruction the processor first take the
instruction from memory.
 The operands and results are also moved between
memory and processor.
 Two basic operations are involved in memory.
Memory Operation
 Read operation
 To start the read operation the processor
send the address of the memory and a
request that it’s contents to be read.
Copy the content. The memory content doesn’t change.
Load (or Read or Fetch)
Instruction and Instruction Sequencing
 Register Transfer Notation
 Assembly-Language Notation
 RISC and CISC Instruction Sets
 Introduction to RISC Instruction Sets
 Instruction Execution and Straight-Line Sequencing
 Branching
Must-Perform Operations

 A computer have instructions capableof

performing 4 types of must operations.
 Data transfers between the memory and the
processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers
Basic Notations:
Register Transfer Notation
 We will see the transformation from one
location in a computer to the other. Possible
locations are memory locations, processor
registers, registers in the I/O sub system.
 Such locations are assigned with convenient
names.
 Eg: memory locations Loc, PLACE, A, var1
Predefined names for processor registers may be R0,
R1, R2 etc..

Contents of any location are represented with square

brackets.

Identify a location by a symbolic name standing for its

hardware binary address (LOC, R0,…)

Contents of a location are denoted by placing square

brackets around the name of the location (R1←[LOC],
R3 ←[R1]+[R2]).

Register Transfer Notation (RTN)

Assembly Language Notation
 Represent machine instructions and
programs.
 Move LOC, R1
R1 = R1←[LOC]
 Add R1, R2, R3
R3= R3 ←[R1]+[R2]
Instruction specifies an operation to be
performed and the operands involved.

In assembly language ADD, Move, load

etc are called mnemonics.

Mnemonics are the words that describe

the operations.
This operation transfer an item of information from the
processor to a specific memory location.

To initiate write:
The processor sends the address of desired location to
the memory along with the data to be written into the
location.
Memory uses the address and data perform a write
Store (or Write)
Overwrite the content in memory
RISC and CISC Instruction Sets

One of the most important characteristics that

distinguish different computers is the nature of their
instructions.

There are two fundamentally different approaches in the

design of instruction sets for modern computers.
 RISC and CISC Instruction Sets

RISC: Reduced Instruction set Computer

CISC: Complex Instruction set Computer

RISC Characteristics:
Relatively few instructions
Relatively few addressing modes.
More accesses are limited to load and store
instructions.
All operations are done with the registers of the CPU.
It is designed to reduce the execution time by
simplifying the instruction set computer.
Each instruction requires only one clock cycle.
Two key characteristics of RISC instruction sets
are:
• Each instruction fits in a single word.
• A load/store architecture is used, in which
– Memory operands are accessed only using Load and
Store instructions.
– All operands involved in an arithmetic or logic operation
must either be in processor registers, or one of the
operands may be given explicitly within the instruction
word.
Introduction to RISC Instruction SETs

C=A+B:

Load R2,A
Load R3,B
Add R4,R2,R3
Store R4,C
Load destination, source

Load processor_register, memory_location

Add is a three-operand, or a three-address,

instruction of the form Add destination, source1,
source2
Instruction Execution and Straight-
Line Sequencing
Connection Between the
Processor and the Memory
Memory

MAR MDR
Control

PC R0

R1
Processor
IR

ALU
Rn - 1

n general purpose
registers

Figure 1.2. Connections between the processor and the memory.

 Let us consider how this program is executed.
 The processor contains a register called the program counter
(PC), which holds the address of the next instruction to be
executed.
 To begin executing a program, the address of its first instruction
(i in our example) must be placed into the PC.

 the processor control circuits use the information in the PC to

fetch
 and execute instructions, one at a time, in the order of
increasing addresses.
 This is called straight-line sequencing. During the execution of
each instruction, the PC is incremented by 4 to point to the next
instruction.
 Executing a given instruction is a two-phase procedure.

 In the first phase, called instruction fetch, the instruction is

fetched from the memory location whose address is in
the PC.
 This instruction is placed in the instruction register (IR) in the
processor.
 At the start of the second phase, called instruction execute,
the instruction in IR is examined to determine which
operation is to be performed.
 The specified operation is then performed by the processor.
 This involves a small number of steps such as fetching
operands from the memory or from processor registers,
performing an arithmetic or logic operation, and
storing the result in the destination location.
A program adding n numbers without Branching
We now introduce branch instructions. This type of
instruction loads a new address into the program counter.

As a result, the processor fetches and executes the

instruction at this new address, called the branch target
instead of the one in sequence.

A conditional branch instruction causes a branch only if a

specified condition is satisfied.

If the condition is not satisfied, the PC is incremented in the

normal way, and the next instruction in sequential address
order is fetched and executed.

Branch_if_[R2]>0 LOOP
Branching
One way of implementing conditional branch instructions
is to compare the contents of two registers and then
branch to the target instruction if the comparison meets
the specified.

For example, the instruction that implements the action

Branch_if_[R4]>[R5] LOOP
may be written in generic assembly language as
Branch_greater_than R4, R5, LOOP
or using an actual mnemonic as
BGT R4, R5, LOOP
Addressing Modes

The way in which memory operand is addressed is called

Addressing modes.

Def: The term addressing modes refers to the way in which the
operand of an instruction is specified.
Basic Addressing Modes
Immediate Mode: Actual data is specified as part
of the instruction. i.e. instruction as an operand field
rather than as address field. The operand field
contains the actual operand.

ADD R4, R6,#200

Register Mode:
Register name is specified as part of the instruction,
i.e. register contains actual data i.e operands i.e
operands are in registers.

ADD R4,R2,R3
Absolute mode (or) Direct Addressing mode:

Memory address is specified as a part of the

instruction, this memory location contains the actual
value.

i.e. The operand resides in the memory and its

address is specified in the address field of the
instruction.

Load R2, Num1

Indirect Addressing

The address field of the instruction specifies the

address of the memory location.

That contains the effective address of the

operand. Two references to memory are required
to fetch the operand.

ADD R1, (A)

Register Indirect Addressing Mode
Register name is specified as part of the instruction.
That register contains the address of the operand in
the memory.

i.e The register contains the address of the operand

rather than the operand.

Load R2, (R3)

Few addressing modes requires that the address field of the
instruction to be added to the content of a specific registers in
the CPU.

Effective Address = Address part of the instruction + Content

of CPU register.

The CPU registers may be PC, index registers or base

registers.

Relative Addressing Mode:

In this effective address of the operand is obtained
by adding the content of PC with address part of
the instruction.
EA = X + (PC)
Indexed Addressing Mode:
In this addressing mode the content of an index register
is added to the address part of the instruction to obtain
the effective address.

Index register is a CPU register that contains an index

value. Here X denotes the constant value contained in
the instruction and Ri is the name of the register involved.

The effective operand is given by E.A= X+[Ri]

Here X may be given either as an explicit number (or) a

symbolic name representing numeric value.
Base with Index
Effective Address is the sum of the contents of the
register Ri and Rj.

The second register is called base register.

ADD R2, [Ri+Rj]

Auto Increment and Auto Decrement mode:

The E.A of an operand is the contents of a register
specified in the instruction.
After accessing the operand, contents of this register is
automatically incremented by 1.

ADD R1, (R2) +

Stacks
A stack is a list of data elements or words.
LIFO
Push, Pop, Top
It is a storage structure that stores information
in the format of LIFO.
It is a group of memory locations with the
register that holds the address of the top of the
element.
The register that holds the address of the top
element of the stack is called Stack pointer (SP)
Stack can be implemented in two ways.
Register Stack
Memory Stack

Memory Stack: Code segment, Data Segment,

Stack

Push: SP <- SP-1

M[SP] <- DR

Substract SP, SP, #4

Store Rj, (SP)

New item to be pushed on the stack is in

processor register Rj
POP:
DR <- M[SP}
SP <- SP+1

Load Rj, (SP)

ADD SP,SP, #4

Load the top value from the stack into

register Rj and increment the SP by 4.
Most of the computers do not provide hardware
to check stack full (or) empty.

The stack limits can be checked by using two

processor registers. One to hold the upper limit
and other to hold lower limit.

Before push,SP is compared with upper limit.

After PoP, SP is compared with lower limit.

Subroutines
It is a set of instructions which are used repeatedly in a
program is called subroutine. (OR)
The block of instructions which carries out a specific
and well defined task is called subroutine.

Need of subroutines.
Some space is allocated for subroutines
When a subroutine is called, PC is jumped to the
starting address of the subroutine.
Before it jumps the present PC value is stored in a link
register.
After execution of subroutine, when a return statement
appears the link register’s value is placed in PC.
Subroutine Call and Return
The way in which a computer makes it possible to call
and return from subroutines is referred to as its subroutine
linkage method.

The simplest subroutine linkage method is to save the

return address in a specific location, which may be a
register dedicated to this function.

Such a register is called the link register.

When the subroutine completes its task, the Return

instruction returns to the calling program by branching
indirectly through the link register.
The Call instruction is just a special branch instruction that
performs the following operations:

• Store the contents of the PC in the link register

• Branch to the target address specified by the Call instruction

The Return instruction is a special branch instruction that

performs the operation

• Branch to the address contained in the link register

Subroutine Nesting
The one subroutine calls another.

In nested calls the link register will be overwritten,

so stack is used for this purpose.
Parameter Passing
When calling a subroutine, the program must provide
parameters to the subroutine to be used in the computation.
Later, the subroutine returns other parameters, which are
the results of the computation.
This exchange of information between a calling program
and a subroutine is referred to as parameter passing.

Parameter passing may be accomplished in several ways.

 The parameters may be placed in registers or in memory
locations, where they can be accessed by the subroutine.

 Alternatively, the parameters may be placed on the

processor stack.
 Passing parameters through processor registers is
straightforward and efficient.

 program for adding a list of numbers can be

implemented as a subroutine, LISTADD, with the
parameters passed through registers.

 The size of the list, n, contained in memory location N,

and the address, NUM1, of the first number, are passed
through registers R2 and R4.

 The sum computed by the subroutine is passed back to

the calling program through register R3.
Parameters Passes through Registers
Disadvantage:
f many parameters are involved, there may not be enough
general-purpose registers available for passing them to the
subroutine.

Alternate method:
The processor stack provides a convenient and flexible
mechanism for passing an arbitrary number of parameters.

Assume that before the subroutine is called, the top of the

stack is at level 1.

The calling program pushes the address NUM1 and the

value n onto the stack and calls subroutine LISTADD.

The top of the stack is now at level 2.

The subroutine uses four registers while it is being
executed.

Since these registers may contain valid data that belong

to the calling program, their contents should be saved at
the beginning of the subroutine by pushing them onto the
stack.

The top of the stack is now at level 3.

Parameters passed on the Stack
The Stack Frame

During execution of the subroutine, six locations at

the top of the stack contain entries that are needed
by the subroutine.

These locations constitute a private work space for

the subroutine, allocated at the time the subroutine
is entered and deallocated when the subroutine
returns control to the calling program.

Such space is called a stack frame.

If the subroutine requires more space for local

memory variables, the space for these variables can
also be allocated on the stack.
Shows an example of a commonly used layout for
information in a stack frame.

In addition to the stack pointer SP, it is useful to have

another pointer register, called the frame pointer (FP),
for convenient access to the parameters passed to the
subroutine and to the local memory variables used by
the subroutine.
 Additional
Instructions
Logical Shifts
 Logical shift – shifting left (LShiftL) and shifting right
(LShiftR)
C R0 0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(a) Logical shift left LShiftL #2,R0

0 R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 0 0 0 1 1 1 0 . . . 0 1

(b) Logical shift right LShiftR #2,R0

Arithmetic Shifts

R0 C

before: 1 0 0 1 1 . . . 0 1 0 0

after: 1 1 1 0 0 1 1 . . . 0 1

(c) Ar ithmetic shift right AShiftR #2,R0

 C R0

. . .

Rotate
before: 0 0 1 1 1 0 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 1

(a) Rotate left without carry RotateL #2,R0

C R0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(b) Rotate left with carry RotateLC #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 1 0 1 1 1 0 . . . 0 1

(c) Rotate right without carry RotateR #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 0 0 1 1 1 0 . . . 0 1

(d) Rotate right with carry RotateRC #2,R0

Figure 2.32. Rotate instructions.

Encoding of
Machine
Instructions
Encoding of Machine Instructions