Gate-Level Minimization

Chapter 3

Digital Circuits
3-1 Introduction
• Gate-level minimization refers to the design task of finding an optimal
gate-level implementation of Boolean functions describing a digital
circuit.

3-2
Digital Circuits
3-2 The Map Method
• The complexity of the digital logic gates
• the complexity of the algebraic expression
• Logic minimization
• algebraic approaches: lack specific rules
• the Karnaugh map
• a simple straight forward procedure
• a pictorial form of a truth table
• applicable if the # of variables < 5
• If there are more than 5 variables, it is still possible to use Karnaugh maps, and you will find larger
Karnaugh maps discussed in many textbooks. However, as the number of variables increases it
becomes more difficult to see patterns, and computer methods start to become more attractive.
• A diagram made up of squares
• each square represents one minterm

3-3
Digital Circuits
• Boolean function
• sum of minterms
• sum of products (or product of sum) in the simplest form
• a minimum number of terms
• a minimum number of literals
• The simplified expression may not be unique

3-4
Digital Circuits
Two-Variable Map
• A two-variable map
• four minterms
• x' = row 0; x = row 1
• y' = column 0;
y = column 1
• a truth table in square
diagram
• xy
• x+y =

Fig. 3.2 Representation of functions

in the map Digital Circuits
3-5
A three-variable
• eight minterms map
• the Gray code sequence
• any two adjacent squares in the map differ by only on
variable
• primed in one square and unprimed in the other
• e.g., m5 and m7 can be simplified
• m5+ m7 = xy'z + xyz = xz (y'+y) = xz

3-6
Digital Circuits
• Example 3-1
• F(x,y,z) = (2,3,4,5)
• F = x'y + xy'

3-7
Digital Circuits
• m0 and m2 (m4 and m6) are adjacent
• m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
• m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'

3-8
Digital Circuits
• Example 3-2
• F(x,y,z) = (3,4,6,7) = yz+ xz'

3-9
Digital Circuits
• Four adjacent squares
• 2, 4, 8 and 16 squares
• m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz'
= x'z'(y'+y) +xz'(y'+y)
= x'z' + xz‘ = z'
• m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz
=x'z(y'+y) + xz(y'+y)
=x'z + xz = z

3-10
Digital Circuits
• Example 3-3
• F(x,y,z) = (0,2,4,5,6)
• F = z'+ xy'

3-11
Digital Circuits
• Example 3-4
• F = A'C + A'B + AB'C + BC
• express it in sum of minterms
• find the minimal sum of products expression

3-12
Digital Circuits
3-3 Four-Variable
• The map Map
• 16 minterms
• combinations of 2, 4, 8, and 16 adjacent squares

3-13
Digital Circuits
• Example 3-5
• F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14)

 F = y'+w'z'+xz'

3-14
Digital Circuits
• Example 3-6 Simplify the Boolean function

F = ABC + BCD + ABCD + ABC

3-15
Digital Circuits
• Prime Implicants
• all the minterms are covered
• minimize the number of terms
• a prime implicant: a product term obtained by combining the maximum
possible number of adjacent squares (combining all possible maximum
numbers of squares)
• essential: a minterm is covered by only one prime implicant, that prime
implicant is called essential

3-16
Digital Circuits
 Consider F ( A, B, C , D )   (0, 2,3,5,7,8,9,10,11,13,15)
• the simplified expression may not be unique
• F = BD+B'D'+CD+AD = BD+B'D'+CD+AB
= BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'

3-17
Digital Circuits
3-4 Five-Variable Map
• Map for more than four variables becomes
complicated
• five-variable map: two four-variable map (one on the
top of the other)

3-18
Digital Circuits
• Table 3.1 shows the relationship between the number of
adjacent squares and the number of literals in the term.

3-19
Digital Circuits
• Example 3-7
• F = (0,2,4,6,9,13,21,23,25,29,31)

F = A'B'E'+BD'E+ACE 3-20
Digital Circuits
 Another Map for Example 3-7

3-21
Digital Circuits
3-5 Product of Sums Simplification
• Approach #1
• Simplified F' in the form of sum of products
• Apply DeMorgan's theorem F = (F')'
• F': sum of products => F: product of sums
• Approach #2: duality
• combinations of maxterms (like it was minterms)
• M0M1 = (A+B+C+D)(A+B+C+D') CD = (A+B+C)+(DD')
AB 00 01
= A+B+C 11 10
00 M0 M1 M3 M2
01 M4 M5 M7 M6
11 M12 M13 M15 M14
10 M8 M9 M11 M10
3-22
Digital Circuits
• Example 3-8
• F = (0,1,2,5,8,9,10)

• F' = AB+CD+BD'
• Apply DeMorgan's theorem; F=(A'+B')(C'+D')(B'+D)
• Or think in terms of maxterms
3-23
Digital Circuits
• Gate implementation of the function of Example 3-
8

3-24
Digital Circuits
• Consider the function defined in
Table 3.2.

In sum-of-minterm:
F ( x, y , z )   (1,3, 4,6)

In product-of-maxterm:

F ( x, y, z )   (0, 2, 5, 7)

3-25
Digital Circuits
• Consider the function defined in
Table 3.2.
F ( x, y , z )  xz  xz 

Combine the 1’s:

F  xz  xz 
Combine the 0’s :

F   xz  xz 
Taking the complement of F
F ( x, y , z )  ( x  z )( x  z )
3-26
Digital Circuits
3-6 Don't-Care Conditions
• The value of a function is not specified for certain combinations of
variables
• BCD; 1010-1111: don't care
• The don't care conditions can be utilized in logic minimization
• can be implemented as 0 or 1
• Example 3-9
• F (w,x,y,z) = (1,3,7,11,15)
• d(w,x,y,z) = (0,2,5)

3-27
Digital Circuits
 • F = yz + w'x'; F = yz + w'z
• F = (0,1,2,3,7,11,15) ; F = (1,3,5,7,11,15)
• either expression is acceptable

• Also apply to products of sum

3-28
Digital Circuits
3-7 NAND and NOR Implementation
• NAND gate is a universal gate
• can implement any digital system

3-29
Digital Circuits
• Two graphic symbols for a NAND gate

3-30
Digital Circuits
Two-level Implementation
• two-level logic
• NAND-NAND = sum of products
• Example: F = AB+CD
• F = ((AB)' (CD)' )' =AB+CD

Fig. 3-20
Three ways to implement
F = AB + CD

3-31
Digital Circuits
• Example 3-10

F ( x, y , z )   (1, 2,3, 4,5,7) F ( x, y , z )  xy   xy  z

3-32
Digital Circuits
• The procedure
• simplified in the form of sum of products
• a NAND gate for each product term; the inputs to each NAND gate are the
literals of the term
• a single NAND gate for the second sum term

3-33
Digital Circuits
Multilevel NAND
• Boolean Circuits
function implementation
• AND-OR logic => NAND-NAND logic
• AND => NAND + inverter
• OR: inverter + OR = NAND

Fig. 3.22
Implementing F = A(CD + B) + BC Digital Circuits
3-34
NAND Implementation

Fig. 3.23
Implementing
F = (AB +AB)(C+ D)
3-35
Digital Circuits
NOR Implementation
• NOR function is the dual of NAND function
• The NOR gate is also universal

3-36
Digital Circuits
 • Two graphic symbols for a NOR gate

Example: F = (A + B)(C + D)E

Fig. 3.26
Implementing
F = (A + B)(C + D)E 3-37
Digital Circuits
Example: F = (AB +AB)(C + D)

Fig. 3.27
Implementing F = (AB +AB)(C + D) with NOR gates
3-38
Digital Circuits
 • Boolean-function implementation
• OR => NOR + INV
• AND
• INV + AND = NOR

第三版內容，參考用 !

3-39
Digital Circuits
第三版內容，參考用 !

3-40
Digital Circuits
第三版內容，參考用 !

3-41
Digital Circuits
3-8 Other Two-level Implementations
• Wired logic
• a wire connection between the outputs of two gates
• open-collector TTL NAND gates: wired-AND logic
• the NOR output of ECL gates: wired-OR logic

F  ( AB )  (CD )  ( AB  CD )  ( A  B)(C   D) AND-OR-INVERT function

F  ( A  B )  (C  D )  [( A  B )(C  D )] OR-AND-INVERT function

3-42
Digital Circuits
Nondegenerate Forms
• 16 possible combinations of two-level forms
• eight of them: degenerate forms = a single operation
• The eight nondegenerate forms
• AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND,
OR-NAND, AND-NOR
• AND-OR and NAND-NAND = sum of products
• OR-AND and NOR-NOR = product of sums
• NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?

3-43
Digital Circuits
AND-OR-Invert Implementation
• AND-OR-INVERT (AOI) Implementation
• NAND-AND = AND-NOR = AOI
• F = (AB+CD+E)'
• F' = AB+CD+E (sum of products)

• simplify F' in sum of products

3-44
Digital Circuits
• OR-AND-INVERT (OAI) Implementation
• OR-NAND = NOR-OR = OAI
• F = ((A+B)(C+D)E)'
• F' = (A+B)(C+D)E (product of sums)

• simplified F' in products of sum

3-45
Digital Circuits
Tabular Summary and Examples
• Example 3-11
• F' = x'y+xy'+z (F': sum of products)
• F = (x'y+xy'+z)' (F: AOI implementation)

• F = x'y'z' + xyz' (F: sum of products)

• F' = (x+y+z)(x'+y'+z) (F': product of sums)
• F = ((x+y+z)(x'+y'+z))' (F: OAI)

3-46
Digital Circuits
Tabular Summary and Examples

3-47
Digital Circuits
 3-48
Digital Circuits
3-9 Exclusive-OR Function
• Exclusive-OR (XOR)
• xy = xy'+x'y
• Exclusive-NOR (XNOR)
• (xy)' = xy + x'y'
• Some identities
• x0 = x
• x1 = x'
• xx = 0
• xx' = 1
• xy' = (xy)'
• x'y = (xy)'
• Commutative and associative
• AB = BA
• (AB) C = A (BC) = ABC
3-49
Digital Circuits
• Implementations
• (x'+y')x + (x'+y')y = xy'+x'y = xy

3-50
Digital Circuits
Odd function
• ABC = (AB'+A'B)C' +(AB+A'B')C =
AB'C'+A'BC'+ABC+A'B'C = (1,2,4,7)
• an odd number of 1's

3-51
Digital Circuits
• Logic diagram of odd and even functions

3-52
Digital Circuits
• Four-variable Exclusive-OR function
• ABCD = (AB’+A’B)(CD’+C’D) =
(AB’+A’B)(CD+C’D’)+(AB+A’B’)(CD’+C’D)

3-53
Digital Circuits
Parity Generation andandChecking
• Parity Generation Checking
• a parity bit: P = xyz
• parity check: C = xyzP
• C=1: an odd number of data bit error
• C=0: correct or an ever # of data bit error

3-54
Digital Circuits
Parity Generation and Checking

3-55
Digital Circuits
Parity Generation and Checking

3-56
Digital Circuits
 3.10 Hardware Description Language
(HDL)

• Describe the design of digital systems in a textual form

• hardware structure
• function/behavior
• Timing
• VHDL and Verilog HDL

3-57
Digital Circuits
A Top-Down Design Flow
第三版內容，參考用 ! Specification

RTL design and

Simulation

Logic Synthesis

Gate Level Simulation

ASIC Layout FPGA Implementation

3-58
Digital Circuits
 Module Declaration

• Examples of keywords:
module, end-module, input, output, wire, and, or, and not.

Fig. 3-37
Circuit to demonstrate an HDL
3-59
Digital Circuits
HDL Example 3.1
• HDL description for circuit shown in Fig. 3.37

3-60
Digital Circuits
 Gate Displays
Example: timescale directive
‘timescale 1 ns/100ps

3-61
Digital Circuits
HDL Example 3.2
• Gate-level description with propagation delays for circuit shown in Fig. 3.37

3-62
Digital Circuits
 HDL Example 3.3
• Test bench for simulating the circuit with delay

3-63
Digital Circuits
Simulation output for HDL Example 3.3

3-64
Digital Circuits
 Boolean Expression
 Boolean expression for the circuit of Fig. 3.37

 Boolean expression:

HDL Example 3.4

3-65
Digital Circuits
HDL Example 3.4

3-66
Digital Circuits
 User-Defined Primitives
 General rules:

 Declaration:

Implementing the hardware in Fig. 3.39

3-67
Digital Circuits
HDL Example 3.5

3-68
Digital Circuits
HDL Example 3.5 (Continued)

3-69
Digital Circuits
Fig. 3.39
Schematic for circuit with_UDP_02467

3-70
Digital Circuits