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Mano6e ch02

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5 views28 pages

Mano6e ch02

Uploaded by

chuanyiceng9539
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Design

With an Introduction to the Verilog HDL, VHDL, and


SystemVerilog
6th Edition

Chapter 02
Boolean Algebra and Logic Gates

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.1
Postulates and Theorems of Boolean Algebra.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.2
Truth Tables for F1 and F2.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.1
Logic diagram for the Boolean function F1 = x + y'z.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.2
Implementation of Boolean function F2 with gates.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Practice Exercise 2.3

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure PE2.4

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.3
Minterms and Maxterms for Three Binary Variables.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.4
Functions of Three Variables.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.5
Truth Table for F = A + B'C.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.6
Truth Table for F = xy + x'z.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.3
Two-level implementation.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.4
Three- and two-level implementation.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Practice Exercise 2.12

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.7
Truth Tables for the 16 Functions of Two Binary Variables.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Table 2.8
Boolean Expressions for the 16 Functions of Two Variables.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.5
Digital logic gates.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.6
Demonstrating the nonassociativity of the NOR
operator: (x ↓ y) ↓ z ≠ x ↓(y ↓ z).

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.7
Multiple-input and cascaded NOR and NAND gates.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.8
Three-input exclusive-OR gate.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.9
Signal assignment and logic polarity.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure 2.10
Demonstration of positive and negative logic.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Practice Exercise 2.13

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Problem 2.15

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Table P2.27

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Figure P2.28

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Figure P2.32

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,


Figure P2.33

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,

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