Computer Organization

21IST34
Module 3

Prepared by
MOHAN D N
Assistant Professor
Department of ISE ,NCET
Bengaluru
Functional Units
Functional Units
Arithmet
Input ic
and
logic
Memory

Output Control

I/O Processo
r

Figure 1.1.Basic functional units of a

computer.
 Information Handled by a Computer

 Instructions/machine instructions
 Govern the transfer of information within a
computer as well as between the computer and
its I/O devices
 Specify the arithmetic and logic
operations to be performed
 Program
 Data
 Used as operands by the instructions
 Source program
 Encoded in binary code – 0 and
1
Memory Unit
 Store programs and data
 Two classes of storage
 Primary storage
 Fast
 Programs must be stored in memory while they are being
executed
 Large number of semiconductor storage cells
 Processed in words
 Address
 RAM and memory access time
 Memory hierarchy – cache, main memory
 Secondary storage – larger and cheaper
Arithmetic and Logic Unit (ALU)

 Most computer operations are

executed in ALU of the processor.
 Load the operands into memory –

bring them to the processor – perform

operation in ALU
– store the result back to memory or
retain in the processor.
 Registers

 Fast control of ALU

Control Unit
 All computer operations are controlled by the
control unit.
 The timing signals that govern the I/O
transfers are also generated by the control
unit.
 Control unit is usually distributed
throughout the machine instead of
standing alone.
 Operations of a computer:
 Accept information in the form of programs and data
through an input unit and store it in the memory
 Fetch the information stored in the memory, under
program control,
into an ALU, where the information is processed
 Output the processed information through an output
unit
 The processor : Data Path and
Control

Data
PC Address Register #
Register A
Instructions Bank Address
L
Register #
Instruction Data Memory
Memory U
Register #
Data

 Two types of functional units:

 elements that operate on data values (combinational)
 elements that contain state (state elements)
 Five Execution Steps
Step name Action for R-type Action for Memory- Action for Action for
instructions reference Instructions jumps
branches
Instruction fetch IR = MEM[PC]
PC = PC + 4

Instruction decode/ register A = Reg[IR[25-21]]

fetch B = Reg[IR[20-16]]
ALUOut = PC + (sign extend (IR[15-0])<<2)

Execution, address ALUOut = A op B ALUOut = A+sign IF(A==B) Then PC=PC[31-

computation, branch/jump extend(IR[15-0]) PC=ALUOut 28]||(IR[25-
completion 0]<<2)

Memory access or R-type Reg[IR[15-11]] = Load:MDR =Mem[ALUOut]

completion ALUOut or
Store:Mem[ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] =

MDR
Basic Operational
Concepts
Review
 Activity in a computer is governed by
instructions.
 To perform a task, an appropriate
program consisting of a list of
instructions is stored in the memory.
 Individual instructions are brought from the
memory into the processor, which executes
the specified operations.
 Data to be used as operands are also stored
in the memory.
A Typical Instruction
 Add LOCA, R0
 Add the operand at memory location LOCA
to the operand in a register R0 in the
processor.
 Place the sum into register R0.
 The original contents of LOCA are
preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into
the processor – the operand at LOCA is
fetched and added to the contents of R0 –
the resulting sum is stored in register R0.
Separate Memory Access and ALU
Operation
 Load LOCA, R1
 Add R1, R0

 Whose contents will be

overwritten?
Connection Between the Processor
and the Memory
Registers
 Instruction
register (IR)
 Program counter (PC)

 General-purpose register (R –
0
Rn-1)
 Memory address register (MAR)
 Memory data register (MDR)
Typical Operating Steps
 Programs reside in the memory through
input devices
 PC is set to point to the first instruction
 The contents of PC are transferred to

MAR
 A Read signal is sent to the memory
 The first instruction is read out and
loaded into MDR
 The contents of MDR are transferred

to IR
 Decode and execute the instruction
Typical Operating Steps (Cont’)

 Get operands for ALU

 General-purpose register
 Memory (address to MAR – Read – MDR to
ALU)
 Perform operation in ALU
 Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR –
Write)
 During
the execution, PC is
incremented to the next
Interrupt
 Normal execution of programs may be
preempted if some device requires urgent
servicing.
 The normal execution of the current
program must be interrupted – the device
raises an interrupt signal.
 Interrupt-service routine
 Current system information backup and
restore (PC, general-purpose registers,
control information, specific information)
Bus Structures
 There are many ways to connect
different parts inside a computer
together.
 A group of lines that serves as a

connecting path for several devices is

called a bus.
 Address/data/control
Bus Structure
 Single-

bus
Speed Issue
 Different devices have
different transfer/operate
speed.
 If the speed of bus is bounded by the

slowest device connected to it, the

efficiency will be very low.
 How to solve this?

 A common approach – use buffers.

Performance
Performance
 The most important measure of a
computer is how quickly it can execute
programs.
 Three factors affect performance:
 Hardware design
 Instruction set
 Compiler
Performance
 Processor time to execute a program depends on the
hardware
involved in the execution of individual machine
instructions.
Main Cache
memory memory Processor

Bu
s

Figure 1.5. The processor

cache.
Performance
 The processor and a relatively small
cache memory can be fabricated on
a single integrated circuit chip.
 Speed

 Cost

 Memory management
Processor Clock
 Clock, clock cycle, and clock rate
 The execution of each instruction is

divided into several steps, each of

which completes in one clock cycle.
 Hertz – cycles per second
Basic Performance Equation
 T – processor time required to execute a program that
has been
prepared in high-level language
 N – number of actual machine language instructions
needed to
complete the execution (note: loop)
 S – average number of basic steps needed to
execute one machine instruction. Each step
completes in one clock cycle
 R – clock rate
 Note: these are not independent to each other

N S
T
R
Pipeline and Superscalar Operation

 Instructions are not necessarily executed

one after another.
 The value of S doesn’t have to be the
number of clock cycles to execute one
instruction.
 Pipelining – overlapping the execution of
successive instructions.
 Add R1, R2, R3
 Superscalar operation – multiple
instruction pipelines are implemented
in the processor.
 Goal – reduce S (could become <1!)
Clock Rate
 Increase clock rate
 Improve the integrated-circuit (IC) technology
to make the circuits faster
 Reduce the amount of processing done in one
basic step (however, this may increase the
number of basic steps needed)
 Increases in R that are entirely caused
by improvements in IC technology
affect all aspects of the processor’s
operation equally except the time to
access the main memory.
CISC and RISC
 Tradeoff between N and S
 A key consideration is the use of

pipelining
 S is close to 1 even though the number of
basic steps per instruction may be
considerably larger
 It is much easier to implement efficient
pipelining in processor with simple
instruction sets
 Reduced Instruction Set Computers
(RISC)
Compiler
 A compiler translates a high-level language
program into a sequence of machine
instructions.
 To reduce N, we need a suitable machine
instruction set and a compiler that makes
good use of it.
 Goal – reduce N×S
 A compiler may not be designed for a
specific processor; however, a high-quality
compiler is usually designed for, and with, a
specific processor.
Performance Measurement
 T is difficult to compute.
 Measure computer performance using benchmark programs.
 System Performance Evaluation Corporation (SPEC) selects
and publishes representative application programs for
different application domains, together with test results for
many commercially available computers.
 Compile and run (no simulation)
 Reference computer

time on the reference computer

Running
SPEC rating  Running time on the computer under test
n 1

SP E C rating  (  SP E C i )
n

i1
 Multiprocessors and Multicomputers

 Multiprocessor computer
 Execute a number of different application tasks in parallel
 Execute subtasks of a single large task in parallel
 All processors have access to all of the memory – shared-
memory
multiprocessor
 Cost – processors, memory units, complex interconnection
networks
 Multicomputers
 Each computer only have access to its own memory
 Exchange message via a communication network –
message-
passing multicomputers
Chapter 2. Machine
Instructions
and
Programs
Memory Locations,
Addresses,
and
Operations
Memory Location, Addresses, and
Operation
n
bits
first word
 Memory
second
consists of word
many millions of
•
storage cells, •
•
each of which
can store 1 bit.
i th
 Data is usually word

accessed in n- •
bit groups. n is •
•
called word
length. last
word

Figure Memory
Memory Location, Addresses, and
Operation
 32-bit
word length
32
example bits
b1 b0

•
•
•
b31 b30

Sign bit: b31= 0 for positive

numbers
for negative
b31= 1
numbers
(a) A signed integer
8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

charact charact charact charact
er er er er
(b) Four
Memory Location, Addresses, and
Operation
 To retrieve information from memory, either
for one word or one byte (8-bit), addresses
for each location are needed.
 A k-bit address memory has 2k memory
locations, namely 0 – 2k-1, called memory
space.
 24-bit memory: 224 = 16,777,216 = 16M
(1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240
 Memory Location, Addresses, and
Operation
 Itis impractical to assign distinct
addresses to individual bit locations
in the memory.
 The most practical assignment is to

have successive addresses refer to

successive byte locations in the
memory – byte- addressable
memory.
 Byte locations have addresses 0, 1, 2,

… If word length is 32 bits, they

Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of
the word
Little-Endian: opposite ordering. lower byte addresses are used for the less
significant bytes of the word
addres
Word Byte address Byte
s address
0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k
k k k k k k
2 - 2 -4 2 -3 2- 2 - 1 2 - 2- 2 - 2 2-3 2 -4
4 2 4 1

(a) Big-endian assignment (b) Little-endian

assignment
Memory Location, Addresses, and
Operation
 Address ordering of bytes
 Word alignment
 Words are said to be aligned in memory if
they begin at a byte addr. that is a
multiple of the num of bytes in a word.
 16-bit word: word addresses: 0, 2, 4 , … .
 32-bit word: word addresses: 0, 4, 8 , … .
 64-bit word: word addresses: 0, 8,16,….
 Access numbers, characters, and
character strings
Memory Operation
 Load (or Read or Fetch)
 Copy the content. The memory content doesn’t
change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used
Instruction and
Instruction

Sequencing
“Must-Perform” Operations
 Data transfers between the memory
and the processor registers
 Arithmetic and logic operations on

data
 Program sequencing and control

 I/O transfers
Register Transfer Notation
 Identifya location by a symbolic
name standing for its hardware
binary address (LOC, R0,…)
 Contents of a location are denoted by

placing square brackets around the

name of the location (R1←[LOC], R3
←[R1]+[R2])
 Register Transfer Notation (RTN)
Assembly Language Notation
 Represent machine instructions
and programs.
 Move LOC, R1 = R1←[LOC]

 Add R1, R2, R3 = R3 ←[R1]+

[R2]
CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to
memory quite often
 General Register
 Registers hold operands thus reduce
memory traffic
 Register bookkeeping
 Stack
 Operands and result are always in the
stack
Instruction Formats
 Three-Address Instructions
 ADD R1, R2, R3 R1 ←
R2 + R3
 Two-Address Instructions
 ADD R1, R2 R1 ← R1 + R2
One-Address
 
ADD M Instructions AC ← AC +
 Zero-Address M[AR]
Instructions TOS ← TOS + (TOS –
 ADD 1)
RISC
  LotsInstructions
of registers. Memory is restricted to Load
& Store

Opcode Operand(s) or Address(es)

Instruction Formats
Example: Evaluate (A+B) 
(C+D)
Three-Address
 1. AD R1, A, B ; R1 ← M[A] +
D R2, C, D M[B]
2. AD X, R1, ; R2 ← M[C] +
D R2 M[D]
3. MU ; M[X] ← R1  R2
L
Instruction Formats
Example: Evaluate (A+B) 
(C+D)
 Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 +
M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 +
M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1
Instruction Formats
Example: Evaluate (A+B) 
(C+D)
One-Address
 1. LOAD ; AC ← M[A]
A ; AC ← AC +
2.
3. ADD
STORET M[B]
4.
B
LOAD ; M[T] ← AC
C ; AC ← M[C]
5. ADD ; AC ← AC +
7.
D
STOREX M[D]
6. MUL ; AC ← AC 
T M[T]
 Instruction Formats
Example: Evaluate (A+B) 
(C+D)
Zero-Address
 1. PUSH ; TOS ← A
A ; TOS ← B
2. PUSH ; TOS ← (A +
B B)
3. ADD ; TOS ← C
4. PUSH ; TOS ← D
C ; TOS ← (C +
7. MUL
5. PUSH D)
(C+D)(A+
D
B) ;; TOS
M[X] ←
←
6. ADD
Instruction Formats
Example: Evaluate (A+B) 
(C+D)
 RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. R1, R1, R2 ; R1 ← R1 +
ADD R2
6. R3, R3, R4 ; R3 ← R3 +
ADD R4
8. STOREX, ; M[X] ←
7. R1, R1, R3 ; R1 ← R1 
R1 R1
MUL R3
Using Registers
 Registers are faster
 Shorter instructions
 The number of registers is smaller
(e.g. 32 registers need 5 bits)
 Potential speedup
 Minimize the frequency with which

data is moved back and forth

between the memory and processor
registers.
 Instruction Execution and
Straight-Line
Sequencing Address
Contents
Assumptions:
Begin execution i Move A,R0
here
3- - One memory operand
i+ Add B,R0 instruction
4 program per instruction
Move R0,C segment
i+ - 32-bit word length
8 - Memory is byte
addressable
A - Full memory address
can be directly
specified
B Data in a single-word
the
for
program
instruction
Two-phase
procedure
-Instruction fetch
C
-Instruction
execute
Page 43
Figure 2.8. A program for C   +
 i Move NUM1,R0
i+ Add NUM2,R0

Branching 4
i+
Add NUM3,R0

8 •
•
•
Add NUMn,R0
i + 4n -
4 Move R0,SUM

i + 4n
•
•
•
SUM
NUM
1
NUM •
•
2 •
NUMn

Figure 2.9. A straight-line program for adding n

 Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and
Progra "Next"
add number to R0
m
loop Decrement R1
Branch>0 LOOP
Branch target
Move
R0,SUM
Conditional
branch •
•
•
SUM
N
n
NUM
Figure Using a loop to add n 1
2.10. numbers.
NUM
•
2 •
•
NUMn
Condition Codes
 Condition code flags
 Condition code register / status

register
 N (negative)

 Z (zero)

 V (overflow)

 C (carry)

 Different instructions affect

different flags
Conditional Branch Instructions

 Example: A: 11110000
 A: 1 1 1 1 0 0 +(−B): 1 1 1 0 1 1 0
00 0
11011100
 B: 0 0 0 1 0 1
00 C=1 Z=0
S=1
V=0
Status Bits

Cn-1 A B

Cn ALU
F
V Z S C
Fn-1

Zero Check
Addressing
Modes
Generating Memory Addresses
 How to specify the address of branch
target?
 Can we give the memory operand

address directly in a single Add

instruction in the loop?
 Use a register to hold the address of

NUM1; then increment by 4 on each

pass through the loop.
Addressing Modes

 Implie Opcode Mode ...

d AC is implied in “ADD
 M[AR]” in “One-
Address” instr.
 TOS is implied in “ADD” in “Zero-Address”
instr.
Immediate

The use of a constant in R1, 5”, i.e. R1
“MOV 5 ←
 Register
 Indicate which register holds the
operand
Addressing Modes
 Register Indirect
 Indicate the register that holds the
register that
number holds the
of the R1
operand
MOV R1, (R2)
 Autoincrement R2 = 3
/
Autodecrement R3 = 5
 Access & update in 1 instr.
Direct
 Address
Use the given address to access a
memory location
Addressing Modes
 Indirect Address
 Indicate the memory location that holds
the address of the memory location
that holds the data
AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A
Addressing Modes

 Relative Address
0
 EA = PC + Relative 1
Addr PC = 2 2

100
AR = 100
101
102 1 1 0
Could be Positive or 103 A
Negative 104
(2’s Complement)
 Addressing Modes
 Indexed
 EA = Index Register + Relative
Addr
Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive or
Negative 102 1 1 0
(2’s Complement) 103 A
104
 Addressing Modes
 Base Register
 EA = Base Register + Relative
Addr
Could be Positive or AR = 2
Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array
 Addressing Modes
Name Assembler syntax Addressingfunction
 The
different Immediate #Value Operand = Value
ways in
which the Register Ri EA = Ri
location of Absolute LOC EA = LOC
an operand (Direct)
is specified
in an Indirect (Ri ) EA = [Ri ]
instruction (LOC) EA = [LOC]
are referred Index X(R i) EA = [Ri ] + X
to as
addressing Basewith index (Ri ,Rj ) EA = [Ri ] + [Rj ]
modes.
Base with index X(R i,Rj ) EA = [Ri ] + [Rj ]
and offset
+ X
Relative X(PC) EA = [PC] +
X
Autoincreme (Ri )
+ EA = [Ri ] ;
nt Increment
Autodecreme  (Ri Ri
nt )
Decrement R
Indexing and Arrays
 Index mode – the effective address of the
operand is generated by adding a constant
value to the contents of a register.
 Index register
 X(Ri): EA = X + [Ri]
 The constant X may be given either as an
explicit number or as a symbolic name
representing a numerical value.
 If X is shorter than a word, sign-extension
is needed.
Indexing and Arrays
 In general, the Index mode facilitates
access to an operand whose location
is defined relative to a reference point
within the data structure in which the
operand appears.
 Several variations:

(Ri, Rj): EA = [Ri] + [Rj]

X(Ri, Rj): EA = X + [Ri] + [Rj]
Relative Addressing
 Relative mode – the effective address is
determined by the Index mode using the
program counter in place of the general-
purpose register.
 X(PC) – note that X is a signed number
 Branch>0 LOOP
 This location is computed by specifying it
as an offset from the current value of
PC.
 Branch target may be either before or
after the branch instruction, the offset is
given as a singed num.
Additional Modes
 Autoincrement mode – the effective address of the
operand is the contents of a register specified in the
instruction. After accessing the operand, the contents
of this register are automatically incremented to
point to the next item in a list.
 (Ri)+. The increment is 1 for byte-sized operands, 2
for 16-bit
operands, and 4 for 32-bit operands.
Mov N,R1
 Autodecrement mode: e
-(R i) – decrement first
#NUM1,R Initializati
Mov 2 R0 on
LOOP e (R2)+,R
Clea 0 R1
r LOOP
Add R0,SUM
Decreme
nt
Branch>
Figure 2.16. The Autoincrement
0 Moveaddressing mode used in the program of
Program to
add a list on n
numbers
written as a
subroutine.
Parameters
are passed
through
processor
NOTE
stack : parameter
passing either by pass
by value or pass by
reference

n – is passed by value
(actual value is
passed)

NUM1 – passed by
reference. address is
passed ( not the
actual entries ofFigur
the2.26. Program of Figure 2.16 written as a subroutine; parameters passed on
list but the address
e of
the stack. www.bookspar.com | Website for
students |
first element is VTU NOTES