Hardware Implementation of OTFS Modulation

Using CORDIC Algorithm

Presented by:
Sai Kumar Dora
IISc Bangalore, SPCOM 2024

Authors: Sai Kumar Dora, Himanshu B. Mishra, Manodipan Sahoo and Kapil Yadav
Dept. of Electronics Engineering, IIT (ISM) Dhanbad
 Outline
1. Introduction and Motivation
2. System Model of OTFS
a) Two step approach
b) Direct approach

3. Architecture for OTFS Transceiver

a) Two step approach
b) Direct approach

4. FFT (R2MDC)
5. CORDIC
a) CORDIC Algorithm
b) CORDIC Architecture

6. Simulation Results
7. References

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 Introduction
• Orthogonal Time Frequency Space (OTFS) modulation has shown superior performance compared to OFDM in high-speed
scenarios, leveraging the time-invariant nature of the delay-Doppler channel.
• Unlike OFDM, where symbols are multiplexed in the time-frequency domain, OTFS multiplexes symbols in the delay-Doppler
domain, necessitating a different system model.
• This OTFS transceiver system model can be implement in two methods: the two-step approach and the direct approach.

1. Two-Step Approach[1]:
Transmitter: ISFFT transform Heisenberg transform.
Receiver: SFFT Wigner transform

2. Direct Approach:
Transmitter: IZak transform.
Receiver: Zak transform

1. S. K. Dora, H. B. Mishra, and M. Sahoo, “Low complexity implementation of OTFS transmitter using fully parallel and
pipelined hardware architecture,” J. Signal Process. Syst., vol. 95, no. 8, pp. 955–964, 2023. [Online]. Available:
https://doi.org/10.1007/s11265-023- 01847-x

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 Why Hardware required?
To commercialize any waveform technology for real-time applications, it must
require hardware implementation.

Objective
• The main objective of this work is to develop the OTFS hardware implementation
using two step approach and direct approach (OTFS 2.0) method.
• Compare the hardware performance between these two distinct approaches in terms of
resource utilization, timing and power considerations.

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OTFS Modulation

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 System Model for OTFS
1. Two Step Approach: It involves ISFFT and Heisenberg transform at the transmit side, along with SFFT and Wigner transform at the
receiver.
Transmitter functions:
• ISFFT Transform: .
• Heisenberg Transform: .
Receiver functions:
• Wigner Transform: .
• SFFT Transform: Y.

2. Direct approach: It involves IZak transform at the transmit side, along with Zak transform at the receiver.
Transmitter functions:
•IZak Transform: .
Receiver functions:
• Zak Transform: Y = .
Where n = 0,…,N−1 and m = 0,…, M−1. The transmit window function and receive window function .

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 OTFS Transceiver Architecture using Two Step Approach

ISFFT can operate in two ways:

1. DD domain IFFT DT domain FFT TF domain
2. DD domain FFT FD domain IFFT TF domain
• M×N OTFS transmitter and receiver implementation using two step approach method contains six FFT/IFFT stages.
• In the M×N OTFS transmitter, the first IFFT stage contains M number of N-point IFFT’s, the second FFT stage
contains N number of M-point IFFT’s and the third IFFT stage contains N number of M-point IFFT’s . This structure
mirrors the receiver side, which contains the same stages in reverse order.

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 OTFS Transceiver Architecture using Direct Approach

• M×N OTFS transmitter and receiver implementation using direct approach method contains only two FFT/IFFT
stages.
• In the M×N OTFS transmitter, first IFFT stage contains M number of N-point IFFT’s and at the receiver side,
second FFT stage contains M number of N-point FFT’s.

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Architecture of OTFS Transceiver using Two Step and Direct
Approach Method

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 R2MDC FFT Hardware Architecture

• Radix-2 Multipath Delay Commutator (R2MDC) was probably the most straightforward approach for pipeline
implementation of radix-2 FFT algorithm[1].
• The input sequence has been broken into two parallel data stream flowing forward, with correct distance between
data elements entering the butterfly scheduled by proper delays. Both butterflies and multipliers are in 50%
utilization.
• Here, -2 multipliers, radix-2 butterflies and registers (delay elements) are required.

1. S. K. Dora, H. B. Mishra, and M. Sahoo, “Low complexity implementation of OTFS transmitter using fully
parallel and pipelined hardware architecture,” J. Signal Process. Syst., vol. 95, no. 8, pp. 955–964, 2023.
[Online]. Available: https://doi.org/10.1007/s11265-023- 01847-x
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 CORDIC

• Challenge: Direct implementation of continuous waveforms (trigonometric, exponential, logarithmic) in

hardware is not feasible.

• Applications: Implementation of linear transformations (DFT, DHT, Z-transform and FFT), digital filters
(Orthogonal digital filters, adaptive lattice filters), QR factorization, with applications to Kalman filtering,
linear system solvers, and covariance system solvers. In some cases, CORDIC evolutes rotational functions
more efficiently than MAC.

• A key innovation in FFT architecture: Replacement of twiddle factor multiplication with iterative CORDIC
rotations, resulting in reduced area.

• Concept: To decompose the desired rotation angle () into weighted sum of a set of predefined elementary
rotation angles. Such rotations implemented with shift and adder operations.

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 CORDIC Algorithm
A rotation about the origin produces the following co-ordinates:
.

=
= .
This can be further decomposed
= cos .
We decomposing into a discrete set of angles (, ,… ,… N−1), where = =
Where as N →∞, K = = 0.6073 and

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 n αn = tan−1 (2−n)
CORDIC Iterations Degrees Radians
0 45.00 0.7854
1 26.57 0.4636
=
2 14.04 0.2450
For example, a rotation of 37° = 45-26.565+14.04+7.13-3.58+1.79-0.9+0.45-0.22-0.11 3 7.13 0.1244

Step2: n=1; ;
4 3.58 0.0624
Initial stage:
; 5 1.79 0.0312

Step1: n=0; Step3: n=3; 6 0.90 0.0160

; 5;
7 0.45 0.0080
8 0.22 0.0040
Step4: n=4; ;
Step5: n=5; ; 9 0.11 0.0020
Step6: n=6; ;
Step7: n=7; ;
Step8: n=8; ;
Step9: n=9; ;
Step10:n=10; ;

Output:

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 CORDIC Architecture

• Implementation cost: Each iteration requires,

three adders, two shifters (hardwired connection)
and one look up table for store predefined
elementary rotation angles.
• predefined elementary rotation angles are fit into
the logic =
• Typically with pipeline register after each
iteration results in very high throughput.

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Simulation of Two Step Approach OTFS Transceiver

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Simulation of direct approach OTFS Transceiver

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 Resource Utilization of OTFS
Parameter Two step approach Direct approach Available (7A200TIFFG11561L
(% of utilization) (% of utilization) FPGA)

LUT 91106 (67.69) 27078 (20.12) 134600

FF 72778 (27.03) 25316 (9.40) 269200
IOB 258 (51.60) 258 (51.60) 500

Timing and Power Report for the OTFS

Parameter Two step approach Direct approach

Time period 10 ns 10 ns

Throughput 118.51 Mbps 336.84 Mbps

Worst Negative Slack (WNS) 1.756 ns 2.352 ns

Worst Hold Slack (WHS) 0.132 ns 0.026 ns

Worst Pulse Width Slack (WPWS) 4.5 ns 4.5 ns

Total on Chip Power 2.594 W 0.897 W

Dynamic Power 2.482 W 0.787 W

Static Power 0.112 W 0.110 W

Junction Temp. 28.8 0C 26.3 0C

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 References

1. H. B. Mishra, P. Singh, A. K. Prasad, and R. Budhiraja, “OTFS channel estimation and data detection designs with
superimposed pilots,” IEEE Transactions on Wireless Communications, vol. 21, no. 4, pp. 2258–2274, 2022.
2. S. K. Mohammed, R. Hadani, A. Chockalingam, and R. Calderbank, “OTFS - predictability in the delay- Doppler domain
and its value to communication and radar sensing,” IEEE BITS the Information Theory Magazine, pp. 1–20, 2023.
3. T. Thaj and E. Viterbo, “OTFS modem SDR implementation and experimental study of receiver impairment effects,” in 2019
IEEE International Conference on Communications Workshops (ICC Workshops), 2019, pp. 1–6.
4. Abushattal, S. E. Zegrar, A. Yazgan, and H. Arslan, “A comprehensive experimental emulation for OTFS waveform RF-
impairments,” Sensors, vol. 23, no. 1, p. 38, 2022.
5. A. R. Shadangi, S. S. Das, and I. Chakrabarti, “VLSI architecture for implementing OTFS,” researchsquare, 2023. [6] M.
Isik, M. Nkomo, A. Das, and K. R. Dandekar, “FPGA implementation of OTFS modulation for 6G communication systems,”
2023.
6. S. K. Dora, H. B. Mishra, and M. Sahoo, “Low complexity implementation of OTFS transmitter using fully parallel and
pipelined hardware architecture,” J. Signal Process. Syst., vol. 95, no. 8, pp. 955–964, 2023. [Online]. Available:
https://doi.org/10.1007/s11265-023- 01847-x.
7. S. K. Dora, R. K. Yadav, M. Sahoo, and H. B. Mishra, “VLSI architecture for low complexity zero forcing equalizer in OTFS
modulation,” in 2023 International Conference on Electrical, Electronics, Communication and Computers (ELEXCOM),
2023, pp. 1–6.

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Thank you