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Unit 6

Digital electronics and computer organisation

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23 views22 pages

Unit 6

Digital electronics and computer organisation

Uploaded by

malisatish2005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Logic

&
Computer Organization

CI219

Prof. R.B.Sadigale.
UNIT 6 : Pipelining

Basic Concept—The Ideal Case,

Pipeline Organization, Pipelining Issues,

 Data Dependencies - Operand Forwarding

Handling Data Dependencies in Software

 Memory Delays.
Pipelining Basic Concept

To improve the performance of a CPU we have two options:

1) Improve the hardware by introducing faster circuits.

2) Arrange the hardware such that more than one


operation can be performed at the same time.

 Since there is a limit on the speed of hardware and the cost


of faster circuits is quite high, we have to adopt the
2nd option.
Pipelining Basic Concept
 Pipelining is a process of arrangement of hardware elements of
the CPU such that its overall performance is increased.

 Simultaneous execution of more than one instruction takes


place in a pipelined processor.

 For executing Single Instructions five stages are involved, that


are
1. Fetch
2. Decode
3. Execute
4. Write
Pipelining
Pipelining Basic Concept (contd.,)
 Execution in a Normal processor - Execution sequence of instructions
in a normal processor can be visualized using a space-time diagram.

 For example, consider a processor having 4 stages and let there be 2


instructions to be executed.

 Total Cycle Required to execute 2 instructions = 08 cycles


Pipelining Basic Concept (contd.,)
 Execution in a Pipelined processor - Execution sequence of instructions
in a pipelined processor can be visualized using a space-time diagram.

 For example, consider a processor having 4 stages and let there be 2


instructions to be executed.

 Total Cycle Required to execute 2 instructions = 05 cycles


Pipeline Organization

 The pipeline organization gives the detailed information about ,how the
instructions are executed.

 In the first stage of the pipeline, the program counter (PC) is used to
fetch a new instruction. As other instructions are fetched, execution
proceeds through successive stages.

 At any given time, each stage of the pipeline is processing a different


instruction.

 Information such as register addresses, immediate data, and the


operations to be performed must be carried through the pipeline as each
instruction proceeds from one stage to the next.
Pipeline Organization (Contd.,)
Pipeline Issues

 In an ideal scenario, instructions overlap perfectly in the


pipeline, as depicted in Figure.

 However, there are situations where the ideal overlap


cannot be achieved due to various pipeline issues.
Pipeline Issues

 Data Hazard: Register Dependency


Consider the case of instructions Ij and Ij+1.

1. If the destination register of I j is a source register for Ij+1, a data hazard arises.

2. The result of Ij is not written into the register file until cycle 4.

3. However, Ij+1 requires the updated value of the source operand in cycle 3.

4. If execution proceeds without consideration, the incorrect result will be


obtained.

5. To ensure correctness, Ij+1 must be stalled in the Decode stage for three cycles,

waiting for the updated value.

6. This delay affects subsequent instructions, increasing the total execution time.
Pipeline Issues

 Other Pipeline Hazards

1. Memory Delays: Hazards caused by delays in accessing


memory.

2. Branch Instructions: Hazards arising from branch instructions


that change the program flow.

3. Resource Limitations: Hazards resulting from limited resources,


such as functional units or cache.
Data dependencies
 Data dependencies occur when one instruction depends on the
result of a previous instruction.

 Consider the instructions:

Add R2, R3, #100

Subtract R9, R2, #30.

 The destination register R2 of the Add instruction is a source


register for the Subtract instruction.

 This creates a data dependency, as register R2 carries data from


the first instruction to the second.
Data dependencies (Contd.,)

 Pipelined Execution: Add and Subtract Instructions

 Figure depicts the pipelined execution of the Add and Subtract


instructions.

 The Subtract instruction is stalled for three cycles to delay


reading register R2 until cycle 6 when the updated value is
available.
Operand Forwarding in Pipelining

 Data dependencies in pipelining can lead to pipeline stalls,


delaying instruction execution.

 Operand forwarding is a technique used to alleviate/relieve


pipeline stalls caused by data dependencies.

 By forwarding the required data directly to the dependent


instruction, the pipeline can continue execution without
stalling.
Operand Forwarding in Pipelining (Contd.,)

 Consider the pair of instructions:

Add R2, R3, #100

Subtract R9, R2, #30.

 The pipeline stalls for three cycles to enable the Subtract


instruction to use the updated value in register R2.
Operand Forwarding in Pipelining (Contd.,)
 Operand forwarding allows the desired value to be forwarded from
the end of cycle 3 to the ALU input in cycle 4.

 Figure depicts the pipelined execution with operand forwarding


implemented.

 The arrow indicates that the ALU result from cycle 3 is used as an
input to the ALU in cycle 4.
Handling Data Dependencies in Software
 Data dependencies in a pipeline can be managed by the processor
hardware or by the compiler.

 Processor hardware solutions include stalling the pipeline or using operand


forwarding.

 An alternative approach is to delegate the detection and resolution of data


dependencies to the compiler.

 When the compiler identifies a data dependency between two successive

instructions Ij and Ij+1, it can insert explicit NOP (No-operation) instructions


between them.

 The purpose of NOP instructions is to introduce a delay that allows


Handling Data Dependencies in Software

 Consider the pair of instructions:

Add R2, R3, #100

Subtract R9, R2, #30.

 it can insert explicit NOP (No-operation) instructions between them.


Handling Data Dependencies in Software
Memory Delays
 Memory delays is delays arising from memory accesses can cause
pipeline stalls in the execution of instructions.

 Consider the instructions:

Load R2, (R3)

Subtract R9, R2, #30

 Load instruction may require more than one clock cycle to obtain its
operand from memory.

 This may occur because the requested instruction or data are not
found in the cache, resulting in a cache miss.
Memory Delays (Contd.,)

 A memory access may take ten or more cycles.

 For simplicity, the figure shows only three cycles.

 A cache miss causes all subsequent instructions to be


delayed.

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