Pin Diagram and

Signals
 +5V Supply (pin 40)

Serial Address and Data Bus

Interrupts(6-pins) 16-pins

Control and Status Signal

Reset
, , ALE, Ready
Status:
(6+1)-pin
DMA
Clock
HOLD,
Pin-1,2 and 37
Ground (pin 20)
 Power supply
40
• Pin 40: (+5V)

• Pin 20: (Ground)

• A single 5 Volt DC supply is used as power supply. 20

• All Voltages are measured/specified with reference to

 Clock
•Pin 1: input 1
2
•Pin 2: input
37
•Pin 37: output

•Clock is the timing signal used to synchronize internal and external operations.

• and are used to connect a crystal, RC- or LC-circuit that determine the oscillating frequency.
•The output of the clock generator is divided by 2 and is available at CLK OUT pin.
• So, µP operating at 3.07 MHz uses a crystal of 6.14MHz.
• If 8085A-2 operating at 5 MHz uses a 10MHz crystal.

•Clock out signal is used to synchronize the operation of external devices whenever required.

•8085 uses a clock of 50% duty cycle. Minimum operating frequency is 500kHz.
 Control Signal: ALE
• Pin 30: ALE output

ALE : Address Latch Enable

• This is a high going pulse available in 1st clock cycle (T1) of every M/C.
• It is used to demultiplex Address Data Bus ()
• Enable the external latch that stores the lower byte of address available in 1st
clock cycle only.
• The latch provides the lower byte of address for the whole Machine cycle.
 Address and Address Data Bus

•Pin 21-28: Higher order Bus output

•Pin 12-19: Address Data Bus bi-directional

• carries the higher order byte of 16-bit address.

• serve the dual purpose of transmitting lower 8-bit address and data.
• Time division Multiplexed
• 1st clock cycle address is available
• From 2nd clock cycle, address is withdrawn and made it free for data transfer.

•An 8-bit transparent latch is used to latch the address available only in 1st clock cycle.
• Address is available for the whole Machine cycle from the Latch.
De-multiplexing Address-Data Bus

𝐴𝐷 7 − 𝐴𝐷 0
 74LS373

𝐷7 𝑂7
𝐷6 𝑂6
𝐷5 𝑂5
𝐷4 8-bit Tristate 𝑂4
𝐷3 Latch Buffer 𝑂3
𝐷2 𝑂2
𝐷1 𝑂1
𝐷0 𝑂0

Latch Enable,
Output Enable,
 is de-multiplexed using an 8-bit Latch and ALE signal.

𝑨 𝟏𝟓 − 𝑨 𝟖 Address Bus (Higher Byte) 𝐴 15 − 𝐴8

80
T3
AL
T1 T2 85
µP E 16-bit
Upper Byte of Address EN Address
Address Data
Bus
ALE
Lower Byte of Address 𝑨𝑫 𝟕 − 𝑨𝑫 𝟎
𝐴𝐷7 −𝐴𝐷0 74LS378
(8-bit Latch) Address Bus (Lower Byte) 𝐴7 − 𝐴0

𝑂𝐸

Data Bus D7 − 𝐷 0 Data BUs

 Status Signal
• Pin 29: output
• Pin 33: output
• Pin 34: / output
 Status Signal Cont.

• , are status output signal that indicates the type of M/C in progress.
• It indicates whether the processor is performing
• Opcode Fetch, IO Operation or M/C
• Memory Read, 0 1 1 Opcode Fetch
0 1 0 Memory Read
• Memory Write,
0 0 1 Memory Write
• IO Read, 1 1 0 IO Read
• IO Write, 1 0 1 IO Write
1 1 1 Interrupt Acknowledge
• Serving an external interrupt x 0 0 No External Access
request,
• Or no bus operation (Bus Idle).
 𝐼𝑂 / 𝑀
• / is used to differentiate between IO and Memory operations.
• = 0, the microprocessor is performing memory related operation.
• = 1, the microprocessor is performing I/O related operation.
 Control Signal: ,
•Pin 31: output Write Control
•Pin 32: output Read Control
•Used to perform read or write operation to/from Memory or IO device.
•Used along with control signal to generate
• : Memory Read
Signal Operation
• : Memory Write
0 0 1 Memory Read
• : IO Read 0 1 0 Memory Write
• : IO Write 1 0 1 IO Read
1 1 0 IO Write
Generation of control
signals
 Logic
• Separate read and write signals for memory and IO are generated from , and
signal.
• The truth Table is
Input Output

0 0 1 0 1 1 1
0 1 0 1 0 1 1
1 0 1 1 1 0 1
1 1 0 1 1 1 0
 𝑹𝑫 𝑀𝐸𝑀𝑅

𝑾𝑹
8085
IO/ 𝑀𝐸𝑀𝑊

𝐼𝑂𝑅

𝐼𝑂𝑊
 𝑹𝑫 𝑀𝐸𝑀𝑅

𝑾𝑹
8085
IO/ 𝑀𝐸𝑀𝑊

𝐼𝑂𝑅

𝐼𝑂𝑊
 We may also generate the signals with decoder.

𝑂7
IO/ 𝐴(MSB) 𝑂6 𝐼𝑂𝑊
2
𝑂5 𝐼𝑂𝑅
𝑅𝐷 𝐴 174LS138 𝑂 4
(3-to-8 decoder)
𝑂3
𝑊𝑅 𝐴0 𝑂2 𝑀𝐸𝑀𝑊
𝑂1 𝑀𝐸𝑀𝑅
𝐸𝐸 𝐸 𝑂0
1 2 3

+5 V Supply
 Ready Signal : Ready
• This is a active high signal used to interface slower peripheral device.
• Initiated by an slower external device when read or write signal is received
• When Ready=0, Microprocessor enter to wait state and remain in that state
till Ready signal goes to high.
• When goes high the processor performs the read or write operation as
initiated.
• During the wait state microprocessor remains idle.
Ready=0 : Device not ready for data transfer
Ready=1 : Device ready for data transfer
• Thus the signal is used to interface slower device.
NOTE:
• Microprocessor is a high-speed device.
• Some of the IO devices operates at a low speed in comparison to
Microprocessor.
• Such devices are interfaced with ready signal.
 Interrupts
• There are 5 hardware interrupts.
• Pin 6: input
• Pin 7: input
• Pin 8: input
• Pin 9: input
• Pin 10: input
• The signals are initiated by peripheral device.
• When a peripheral device needs service from Microprocessor it send an electrical
signal through this line.
• On recognizing the interrupt request the microprocessor stop the execution of
the current program, save the status in stack and execute another specific
program to serve the requested device.
• On completion of the service program the processor retrieve the status from
stack and execute the previous program from where it had left.
 Interrupts:
• Pin 11: output

Interrupt Acknowledge signal.

• This is an output signal. When the INTR interrupt is recognized, the processor
acknowledge the request through this line (goes low).
• In response to it, the peripheral device loads the load the location service routine in
the form of instructions.
• RSTn or CALL
• The processor uses the signal as a read signal to read the instruction from the data
bus.

• So, this is also grouped under control signals.

 SERIAL IO
• Pin 4: (Serial Output Data) output
• Pin 5: (Serial Input Data) input
SOD : Serial Output Data
SID : Serial Input Data

• Serial data are received through SID line.

• Transfer the line status to MSB bit of Accumulator when RIM instruction is
executed.
• Serial data are transmitted through SOD line if serial data output is enabled.
• Loads the MSB bit of Accumulator to this line when SIM instruction is
executed.
SIM: Set Interrupt Mask
RIM: Read Interrupt Mask
 RESET
•Pin 36: input
•Pin 3: output

•The Microprocessor resets if the is held low for at least 3 clock cycles. Resetting
microprocessor means:
 It clears the PC and IR i.e. PC=0000H, IR=00H.
 Disabling all interrupts (except TRAP).
 Disabling the SOD pin.
 All the buses (data, address, control) are tri-stated.
 RESET OUT pin goes to high.
 The RESET OUT signal is used to reset external devices when the microprocessor resets.
Resetting a peripheral device means: To bring it back to some predetermined initial
states.
 DMA
DMA : Direct Memory Access
•Pin 39: input
•Pin 38: output
• An external master makes HOLD high to request the processor to release the
SYTEM BUS. The HOLD signal remains high.
• On receiving the request, the processor Acknowledges the Bus request by making
HLDA high.
• The bus is released from the next clock cycle and the processor goes to idle state.
• HOLD and HLDA remains high
• , , , , pins are tri-stated.
• On Completion of the job, external master pulls down HOLD line low indicating
that it is releasing the bus from next clock cycle.
• Microprocessor regain the bus access, pull down HLDA and resume the execution.