Hacettepe University

ELE 225 Fundamentals of Digital

Systems

Chapter 7:
Memory and Programmable Logic

Assoc. Prof. S. Esen Yüksel

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Topics

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 Previously on ELE 225
We learned how to
Analyze and design registers, shift registers, and
universal shift registers in different modes.
 Properly create the effect of a gated clock.
 Analyze and design a serial adder circuit.
Analyze and design a ripple counter, synchronous
counter, ring counter, and Johnson counter.

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 Chapter Objectives
 Know the organizational structure and functionality of
programmable logic devices (PLDs).
 Know how array logic diagrams differ from conventional
logic diagrams.
 Know how to specify and describe a memory unit.
 Know how to interpret memory cycle timing waveforms.
 Know how to differentiate between RAM, ROM, SDRAM,
DRAM.
 Know how to use different methods in memory decoding.
 Know how to use a Hamming code to detect and correct a
single error, and to detect a double error.
 Analyze and design digital circuits with ROM, PLA, and PAL.
 Know how to differentiate between SPLD, CPLD, and FPGA.
 Know the basic architecture of an FPGA.
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 7-1. Introduction
 Two types of memories are used in digital systems:
Random-access memory (RAM): performs both the write
and read operations.

Read-only memory (ROM): performs only the read operation.

 The ROM is a programmable logic device (PLD).
 Other such units are the programmable logic array
(PLA), the programmable array logic (PAL), and the
field-programmable gate array (FPGA).

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 Array logic
 A typical programmable logic device may have
hundreds to millions of gates interconnected through
hundreds to thousands of internal paths.
 So we employ a special gate symbology for array logic.
 A single line enters the gate, and the input lines are
drawn perpendicular.

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 7-2. Random-Access
Memory
 A memory unit stores binary information in groups of bits called words.
1 byte = 8 bits
16 bit word = 2 bytes; 32bit word = 4 bytes etc.

 The communication
between a memory
and its environment is
achieved through data
input and output lines,
address selection
lines, and control lines
that specify the
direction of transfer.
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 Content of a memory
 Each word in memory is
assigned an identification
number, called an address,
starting from 0 up to 2k-1,
where k is the number of
address lines.
 The selection of a specific
word inside memory is
done by applying the k-bit
address to the address
lines.
 An internal decoder accepts
the address and opens the Each address is of 10 bits  k
= 10
paths to select the word. Generating 2^10 = 1024
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 Content of a memory
 It is customary to refer to the number of
words (or bytes) in memory with one of
the letters K (kilo), M (mega), and G
(giga).
 K=210, M=220, or G=230.
 Thus, 64K = 216; 2M = 221; 4G = 232

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 Content of a memory
 Ex: Consider a memory
unit with a capacity of 1K
words of 16 bits each.
 1K = 1,024 = 210 words

 1 word = 16 bits = 2

bytes
 Therefore, the memory

can accommodate 2,048

= 2K bytes

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 Write and Read operations
 RAM can perform read and write
operations.
 Write operation = Transferring a new
word to be stored into memory:
1. Apply the binary address of the desired word to
the address lines.
2. Apply the data bits that must be stored in memory
to the data input lines.
3. Activate the write input.

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 Write and Read operations
 Read operation = Transferring a stored
word out of memory:
1. Apply the binary address of the desired word to
the address lines.
2. Activate the read input.
 The memory unit will then take the bits
from the word that has been selected by
the address and apply them to the output
data lines.

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 Write and Read operations
 Commercial memory sometimes provide the
two control inputs for reading and writing in a
somewhat different configuration in table 7-1.

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 Timing Waveforms
 The operation of the memory unit is controlled by an
external device such as a central processing unit
(CPU).
 The CPU is synchronized by its own clock.
 The memory does not have an internal clock.
 The access time of memory is the time required to
select a word and read it.
 The cycle time of memory is the time required to
complete a write operation.
 The CPU must provide the memory control signals to
synchronize the read and write operations of memory.

This means that the access time and cycle time of the memory
must be within a time equal to a fixed number of CPU clock
cycles.
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 Timing Waveforms (write)
 Ex: Consider a
CPU has a clock
frequency of 50
MHz, i.e. has a
period of 20 ns
for one clock
cycle.
 Suppose the
memory has
cycle and
access time of
50 ns.
 Then the
enable and
read/write
signals must
stay active for
15
at least 50 ns.
 Timing Waveforms (read)
 The memory
places the
word selected
by the address
into the output
data lines
within a 50 ns
interval.
 The CPU can
transfer the
data into one
of its internal
registers
during the
negative
transition of
T3. 16
 Types of memories
 In a random‐access memory, the access time
is always the same regardless of the
particular location of the word.
 In sequential-access memory, the
information the time it takes to access a
word depends on the position of the word
with respect to the position of the read head;
therefore, the access time is variable. Ex: CD

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 Static RAM
 RAMs have two types: Static and Dynamic.
 In SRAM, the stored information remains
valid as long as power is applied to the unit.
 consists of internal latches that store the binary
information.
 SRAM is easier to use and has shorter read
and write cycles.

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 Dynamic RAM
 DRAM stores the binary information in the form
of electric charges on capacitors.
 The capacitors tends to discharge with time and
must be periodically recharged by refreshing
the dynamic memory.
 DRAM offers reduced power consumption and
larger storage capacity in a single memory chip.

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 Types of memories
 Memory units that lose stored information
when power is turned off are said to be
volatile.
 Both static and dynamic, are of this category
since the binary cells need external power to
maintain the stored information.
 Nonvolatile memory, such as magnetic disk,
ROM, retains its stored information after
removal of power.

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 7-3. Memory decoding
 The equivalent logic of a binary cell that stores one bit of
information is shown below.
Read/Write = 0, select = 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R latch

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 4x4 RAM
 There is a need for
decoding circuits to select
the memory word
specified by the input
address.
 During the read operation,
the four bits of the
selected word go through
OR gates to the output
terminals.
 During the write operation,
the data available in the
input lines are transferred
into the four binary cells of
the selected word.
 A memory with 2k words of
n bits per word requires k
address lines that go into
kx2k decoder.
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 Coincident decoding address

 A decoder with k inputs

and 2k outputs requires 2k
AND gates with k inputs
per gate.
 Two decoding in a 2D
selection scheme can
reduce the number of
inputs per gate.
 1K-word memory: instead
of using a single 10x1024
decoder, we use two 5x32
decoders.
 One decoder selects the
row, the other selects the
column.

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 Address multiplexing
 DRAMs typically have four times the density of SRAM
(i.e., four times the memory on a same size chip).
 The cost per bit of DRAM storage is three to four times
less than that of SRAM storage. They also have lower
power consumption. That’s why we prefer DRAMS on
PC’s!
 To reduce the number of pins in the IC package,
address multiplexing is used.
 In a two-dimensional array, the address is applied in
two parts at different times, with the row address first
and the column address second. Since the same set of
pins is used for both parts of the address, it can
decrease the size of package significantly.
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 Address multiplexing for 64K
DRAM
 After a time
equivalent to the
settling time of the
row selection, RAS
goes back to the 1
level.
 Registers are used to
store the addresses of
the row and column.
 CAS must go back to
the 1 level before
initializing another
memory operation.

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 7-4. Error detection and
correction
 There may be errors when storing/retrieving the
binary data to/from memory.
 The most common error detection method is the
parity bit.
 A parity bit is generated and stored along with the data
word in memory.
 The parity of the word is checked after reading it from
memory.
 The data word is accepted if the parity of the bits read
out is correct.
 If the parity checked results in an inversion, an error is
detected, but it cannot be corrected.

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 7-4. Error detection and
correction
 An error‐correcting code generates multiple parity
check bits that are stored with the data word in
memory.
 Each check bit is a parity over a group of bits in the
data word.

When the word is read back from memory, the associated parity
bits are also read from memory and compared with a new set of
check bits generated from the data that have been read.

If the check bits are correct, no error has occurred; if not, they
generate a unique pattern, called a syndrome, that can be
used to identify the bit that is in error.

A single error occurs when a single bit changes during the write
or read operation. If the specific bit in error is identified, then
the error can be corrected by complementing the erroneous bit.

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 Hamming Code
 One of the most common error‐correcting codes
used in RAMs was devised by R. W. Hamming.
 In Hamming code, k parity bits added to n-bit
data word forming a new word of n+k bits.
 The bit positions are numbered in sequence from 1 to
n+k.
 Those positions numbered as a power of 2 are reserved
for the parity bits.
 The remaining bits are the data bits.
 The code can be used with words of any length.

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 Hamming Code
Example: Consider the 8-bit data word 11000100. We
include four parity bits with it and arrange the 12 bits as
follows:
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0

P1 = XOR of bits (3,5,7,9,11) = 1  1  0  0  0 = 0

P2 = XOR of bits (3,6,7,10,11) = 1  0  0  1  0 = 0
P4 = XOR of bits (5,6,7,12) = 1  0  0  0 = 1
P8 = XOR of bits (9,10,11,12) = 0  1  0  0 = 1
 Each parity bit is set so that the total number of 1’s in
the checked positions, including the parity bit, is always
even. 29
30
 Hamming Code
 The 8-bit data is stored in memory together with 4
parity bits as a 12-bit composite word.
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0

 When the 12 bits read from memory, the parity is

checked over the same combination of bits including the
parity bit.
 The 4 check bits are evaluated as follows:
C1 = XOR of bits (1,3,5,7,9,11) (least sign. bit is a 1. : 01, 11, 101..)
C2 = XOR of bits (2,3,6,7,10,11) (sec. sign. bit is a 1. : 10, 11, 110..)
C4 = XOR of bits (4,5,6,7,12)
C8 = XOR of bits (8,9,10,11,12)
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 Hamming Code
 A 0 check bit designates an even parity over the
checked bits and a 1 designates an odd parity.
 Since the bits were stored with even parity, the result,
C = C8C4C2C1 = 0000, indicates that no error has
occurred.
 If C ≠ 0, then the 4-bit binary number (syndrome)
formed by the check bits gives the position of the
erroneous bit.
 The Hamming code can detect and correct only a
single error.
 Some multiple-bit errors are detected, but they may be
corrected erroneously, as if they were single-bit errors. 32
 Hamming Code
 For example, consider the following three cases:
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0 No error
1 0 1 1 1 0 0 1 0 1 0 0 Error in bit 1
0 0 1 1 0 0 0 1 0 1 0 0 Error in bit 5
 Evaluating the XOR of the corresponding bits, we find
the four check bits as follows:
C8 C4 C2 C1
For no error: 0 0 0 0
with error in bit 1: 0 0 0 1
with error in bit 5: 0 1 0 1
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 Hamming Code
 The Hamming Code can
be used for data words of
any length.
 The number of total bits
in Hamming Code is n+k
bits, the syndrome value
C consists of k bits and
has a range of 2k values
between 0 and 2k−1. The
range of k must be equal
to or greater than n+k,
giving the relationship
2k-1 ≥ n + k
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 Hamming Code
 The grouping of bits for parity generation and checking can
be determined from a list of binary numbers from 0 through
2k-1.
 The least significant bit is a 1 in the binary numbers 1,3,5,7 and
so on.
 The second significant bit is a 1 in binary numbers 2,3,6,7, and so
on.

 Comparing these numbers with the bit positions used in

generating and checking parity bits in the Hamming code,
we note the relationship between the bit groupings in the
code and the position of the 1‐bits in the binary count
sequence.
 Each group of bits starts with a number that is a power of 2: 1, 2,
4, 8, 16, etc.
 These numbers are also the position numbers for the parity bits.
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 Single-Error correction, Double-
Error detection
 The Hamming code can detect and correct only a
single error.
 By adding another parity bit to the coded word, the
Hamming code can be used to correct a single
error and detect double errors.
 The previous 12‐bit coded word becomes
001110010100P13.
 P13 is evaluated from the XOR of the other 12 bits.
This produces the 13‐bit word 0011100101001
(even parity).

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 Single-Error correction, Double-
Error detection
 When the 13‐bit word is read from memory, the
check bits are evaluated as usual.
 The parity P is evaluated over the entire 13 bits.
 P = XOR (0011100101001)
 If P=0, then the parity is correct (even parity)
 If P=1, then the parity is incorrect (odd parity).
 The following four cases can arise:
 If C=0 and P=0, no error occurred
 If C≠0 and P=1, a single error occurred that can be
corrected
 If C≠0 and P=0, a double error occurred that is detected
but that cannot be corrected
 If C=0 and P=1, an error occurred in the P13 bit
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 7-5. Read-Only Memory
 A block diagram of a ROM is shown below. It consists of k
address inputs and n data outputs.
 The number of words in a ROM is determined from the fact
that k address input lines are needed to specify 2k words.

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 Construction of ROM
 Each output of the decoder represents a memory address.
 Each OR gate must be considered as having 32 inputs.
 A 2kn ROM will have an internal k2k decoder and n OR gates.

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 Truth table of ROM
 A programmable connection between two lines is logically
equivalent to a switch that can be altered to either be close or
open.
 Intersection between two lines is sometimes called a cross-
point.

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 Programming the ROM
In Table 7-3, 0  no connection
1  connection
Address 3 = 10110010 is permanent storage using fuse link

1 0 1 1 0 0 1 0

 : means connection
41
 Combinational circuit
implementation
 The internal operation of a ROM can be interpreted
in two ways:
 A memory unit that contains a fixed pattern of stored
words.
 A unit which implements a combinational circuit.

 Fig. 7-11 may be considered to be a combinational

circuit with eight outputs, each being a function of
the five input variables.
 The output A7 can be expressed as sum-of
minterms:
A7(I4, I3, I2, I1, I0) = Σ(0,2,3…,29)
42
 Combinational circuit
implementation
 Example: Design a combinational circuit using a ROM. The
circuit accepts a 3-bit number and generates an output binary
number equal to the square of the input number.

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 Combinational circuit
implementation
 We actually need to generate only four outputs with the
ROM; the other two are readily obtained.
 The minimum size of ROM needed must have three inputs
and four outputs  ROM must be of size 84.

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 Types of ROMs
 The required paths in a ROM may be programmed in
four different ways.

Mask programming : fabrication process by the
semiconductor company.

Read-only memory or PROM : blown fuse /fuse intact
by the application of high-voltage pulse.

Erasable PROM or EPROM : erased by ultraviolet
light.

Electrically-erasable PROM(EEPROM) : erased with an
electrical signal
 !!! In any case, all procedures for programming ROMs
are hardware procedures, even though the word
“programming” is used. 45
 Combinational PLDs
 A combinational programmable logic device
(PLD) is an integrated circuit with programmable
gates divided into an AND array and an OR array to
provide an AND-OR sum-of-product
implementation.
 PROM: fixed AND array constructed as a decoder
and programmable OR array.
 PAL: programmable AND array and fixed OR array.
 PLA: both the AND and OR arrays can be
programmed.

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Combinational PLDs

47
 7-6. Programmable Logic
Array
 Fig.7-14, the decoder in PROM is replaced by an
array of AND gates that can be programmed to
generate any product term of the input variables.
 The product terms are then connected to OR gates
to provide the sum of products for the required
Boolean functions.
 The output is inverted when the XOR input is
connected to 1 (since x⊕1 = x’). The output
doesn’t change and connect to 0 (since x⊕0 = x).

48
Fig. 7-14
PLA with 3 Inputs, 4 Product Terms, and 2
Outputs
Ex: implement with PLA
F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

AB’

AC

BC

A’BC
’

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 PLA programming table
F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

First: lists the product terms numerically.

Second: specifies the required paths between inputs and AND gates. True
variable is listed as 1, complemented is 0. Dash if variable is absent from
product.
Third: specifies the paths between the AND and OR gates.
For each output variable, we may have a T(true) or C(complement) for
programming the XOR gate.
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Customer only submits the PLA program table to the manufacturer.
 PLA programming table
 In implementing a combinational circuit with a PLA,
careful investigation must be undertaken in order to
reduce the number of distinct product terms, since a
PLA has a finite number of AND gates.
 This can be done by simplifying each Boolean function to a
minimum number of terms.
 The number of literals in a term is not important, since all
the input variables are available anyway.
 Both the true value and the complement of each
function should be simplified to see which one can
be expressed with fewer product terms and which
one provides product terms that are common to
other functions.
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 PLA Example 7.2
 Example 7.2: Implement the following two Boolean
functions with a PLA.

F1 = A’B’ + A’C’ + F2 = AB + AC +
B’C’ A’B’C’
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F1’ = AB + AC + BC F2’ = A’C + A’B +
 PLA Example 7.2
F1’ = AB + AC + BC F2 = AB + AC +
 A’B’C’
This combination gives a minimum of four distinct
product terms: AB, AC, BC, and A’B’C’ .

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PLA Example 7.2

AB

AC

BC

A’B’
C’

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 7-7. Programmable Array
Logic
 The PAL is a programmable logic device with a fixed OR array
and a programmable AND array.

55
 Programmable Array Logic
 In designing with a PAL, the Boolean functions must
be simplified to fit into each section.
 Unlike the PLA, a product term cannot be shared
among two or more OR gates.
 Therefore, each function can be simplified by itself,
without regard to common product terms.
 The number of product terms in each section is
fixed, and if the number of terms in the function is
too large, it may be necessary to use two sections to
implement one Boolean function.
 The output terminals are sometimes driven by
three‐state buffers or inverters.
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 Example
w(A, B, C, D) = ∑ (2, 12, 13)
x(A, B, C, D) = ∑ (7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑ (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ∑ (1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean

functions:

w = ABC’ + A’B’CD’
x = A + BCD
y = A’B + CD + B’D’
z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ +
A’B’C’D
57
 PAL programming table
 Every 3 rows go into one output

58
Fig. 7-17

59
 7-8. Sequential Programmable
Devices
 Sequential programmable devices include both
gates and flip-flops. Three major types:
 Sequential (or simple) Programmable Logic Device
(SPLD)
 Complex Programmable Logic Device (CPLD)
 Field Programmable Gate Array (FPGA)

60
 Sequential (or simple)
Programmable Logic Device (SPLD)
 The configuration mostly used in an SPLD is the
combinational PAL together with D flip‐flops.
 A PAL that includes flip‐flops is referred to as a
registered PAL, to signify that the device contains
flip‐flops in addition to the AND–OR array.
 Each section of an SPLD is called a macrocell, which
is a circuit that contains a sum‐of‐products
combinational logic function and an optional flip‐flop.
 We will assume an AND–OR sum‐of‐products
function, but in practice, it can be any one of the two‐
level implementations.

61
Sequential (or simple)
Programmable Logic Device (SPLD)

Basic macrocell 62
 Complex Programmable Logic Device
(CPLD)
 A typical SPLD has from 8 to 10 macrocells within
one IC package. All the flip-flops are connected to
the common CLK input and all three-state buffers
are controlled by the OE input.
 The design of a digital system using PLD often
requires the connection of several devices to
produce the complete specification. For this type of
application, it is more economical to use a complex
programmable logic device (CPLD).
 A CPLD is a collection of individual PLDs on a single
integrated circuit.
63
 General CPLD configuration
 CPLD consists of multiple PLDs interconnected
through a programmable switch matrix.
 8 to 16 macrocells per PLD.

General CPLD configuration 64

 Gate Array
 The basic component used in VLSI design
is the gate array.
 A gate array consists of a pattern of gates
fabricated in an area of silicon that is
repeated thousands of times until the
entire chip is covered with the gates.
 Arrays of one thousand to hundred
thousand gates are fabricated within a
single IC chip depending on the
technology used.
65
 Field‐Programmable Gate Array
(FPGA)
 FPGA is a VLSI circuit that can be programmed in
the user’s location.
 An FPGA is more flexible than CPLD, allows more
complex logic implementations.
 A typical FPGA consists of an array of millions of
logic blocks, surrounded by programmable I/O
blocks and connected together via programmable
interconnections.
 A typical FPGA logic block consists of lookup tables,
multiplexers, gates, and flip‐flops.
 Look-up table is a truth table stored in an SRAM and
provides the combinational circuit functions.
66
 Field‐Programmable Gate Array
(FPGA)
 The advantage of using RAM in FPGA instead of ROM
to store the truth table is that the table can be
programmed by writing into memory.
 The disadvantage is that the memory is volatile and
presents the need for the look-up table content to
be reloaded in the event that power is disrupted.

67