USB

Universal Serial Bus (USB) is an industry standard developed through a

collaborative effort of several computer and communication companies,
including Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, Nortel
Networks, and Philips.
Speed
Low-speed(1.5 Mb/s)
Full-speed(12 Mb/s)
High-speed(480 Mb/s)
Port Limitation
Device Characteristics
Plug-and-play
Universal Serial Bus tree structure

Host computer

Root
hub

Hub Hub

Hub I/O I/O I/O I/O

device device device device

I/O I/O
device device
 Universal Serial Bus tree structure
To accommodate a large number of devices that can be added or removed at any time,
the USB has the tree structure as shown in the figure.
Each node of the tree has a device called a hub, which acts as an intermediate control
point between the host and the I/O devices. At the root of the tree, a root hub connects
the entire tree to the host computer. The leaves of the tree are the I/O devices being
served (for example, keyboard, Internet connection, speaker, or digital TV)
In normal operation, a hub copies a message that it receives from its upstream
connection to all its downstream ports. As a result, a message sent by the host
computer is broadcast to all I/O devices, but only the addressed device will respond to
that message. However, a message from an I/O device is sent only upstream towards
the root of the tree and is not seen by other devices. Hence, the USB enables the host
to communicate with the I/O devices, but it does not enable these devices to
communicate with each other.
 Universal Serial Bus tree structure
To accommodate a large number of devices that can be added or removed at any time,
the USB has the tree structure as shown in the figure.
Each node of the tree has a device called a hub, which acts as an intermediate control
point between the host and the I/O devices. At the root of the tree, a root hub connects
the entire tree to the host computer. The leaves of the tree are the I/O devices being
served (for example, keyboard, Internet connection, speaker, or digital TV)
In normal operation, a hub copies a message that it receives from its upstream
connection to all its downstream ports. As a result, a message sent by the host
computer is broadcast to all I/O devices, but only the addressed device will respond to
that message. However, a message from an I/O device is sent only upstream towards
the root of the tree and is not seen by other devices. Hence, the USB enables the host
to communicate with the I/O devices, but it does not enable these devices to
communicate with each other.
 Addressing
 When a USB is connected to a host computer, its root hub is attached to the processor
bus, where it appears as a single device. The host software communicates with
individual devices attached to the USB by sending packets of information, which the
root hub forwards to the appropriate device in the USB tree.
 Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit
address. This address is local to the USB tree and is not related in any way to the
addresses used on the processor bus.
 A hub may have any number of devices or other hubs connected to it, and addresses
are assigned arbitrarily. When a device is first connected to a hub, or when it is
powered on, it has the address 0. The hardware of the hub to which this device is
connected is capable of detecting that the device has been connected, and it records
this fact as part of its own status information. Periodically, the host polls each hub to
collect status information and learn about new devices that may have been added or
disconnected.
 When the host is informed that a new device has been connected, it uses a sequence
of commands to send a reset signal on the corresponding hub port, read information
from the device about its capabilities, send configuration information to the device,
and assign the device a unique USB address. Once this sequence is completed the
device begins normal operation and responds only to the new address.
PCI Bus
 Peripheral Component Interconnect
 Introduced in 1992
 Low-cost bus
 Processor independent
 Plug-and-play capability
 In today’s computers, most memory transfers involve a burst of data rather than just one word. The
PCI is designed primarily to support this mode of operation.
 The bus supports three independent address spaces: memory, I/O, and configuration.
 we assumed that the master maintains the address information on the bus until data transfer is
completed. But, the address is needed only long enough for the slave to be selected. Thus, the
address is needed on the bus for one clock cycle only, freeing the address lines to be used for sending
data in subsequent clock cycles. The result is a significant cost reduction.
 A master is called an initiator in PCI terminology. The addressed device that responds to read and
write commands is called a target.
Data transfer signals on the PCI bus.

Name Function

CLK A 33-MHz or 66-MHz clock.

FRAME# Sent by the initiator to indicate the duration of a

transaction.

AD 32 address/data lines, which may beoptionally

increased to 64.

C/BE# 4
command/byte-enable lines (8 for a 64-bit bus).

IRD Y#, TRD Y# Initiator-ready and Target-readysignals.

DEVSEL# A response from the device indicating that it has

recognized its address and is ready for a data
transfer transaction.

IDSEL# Initialization Device Select.