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Timer and Counter in PLC

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11 views15 pages

Timer and Counter in PLC

Uploaded by

sharmahk2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Timers and Counters in PLC

B.Tech. : Mechanical Engineering,


Year/Semester: III / V
Subject: Mechatronic Systems (5ME3-01)

By:
Praveen Saraswat
Associate Professor
Department of Mechanical Engineering
Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur
Lecture Outcomes

The students will be able to:

• Understand the concept of timers and counters in


PLC controller.

• Apply timers and counters functions in ladder


logic applications.
Introduction
• Timers
• A timer is a PLC instruction measuring the amount of time elapsed following an
event.

• Timer instructions come in two basic types: on-delay timers and off-delay
timers. Both “on-delay” and “off-delay” timer instructions have single inputs
triggering the timed function.

• The accuracy and repeatability of the timer are extremely high because the PLC
processor generates delays.

• A timer starts counting at time-based intervals and continues until the


accumulated value equals the preset value.
 Timers are used to delay actions
 Keep an output on for a specified time after an input turns off

 Keep an output off for a specified time before it turns on

 Timing functions are vital in PLC applications


 Cycle times are critical in many processes

 Many PLCs use block-type timers and counters


 Compliance with IEC 61131-3 standards
Timer Attributes
• Timer
• Time Base
• Preset
• Accumulator
On Delay Timer
• An “on-delay” timer activates an output only when the input has been
active for a minimum amount of time.

• The timer starts operating, when the rung is turned ON.

• When the rung is on, the timer starts counting until the preset value is
equal to the accumulated value.

• The timer starts counting when the rung is turned ON, the counting of
accumulated value will be shown at the ET rung on the timer logic.
Status Bits

• Timer Status bits can be used in ladder logic


• Status Bits (EN, DN, TT)
TON Timer Ladder Diagram
Timer OFF Delay (TOF)
Used to turn an output On or OFF after rung has been
off for a desired time:
• TOF starts to accumulate time when the rung becomes false

• It continues to accumulate time until the accumulated value equals the


preset value or the rung becomes true

• The timer enable bit (EN bit 15) is set when the rung becomes true. It is
reset when the rung becomes false and ACC < PRE or the DN bit is reset
(ACC = PRE)

• The done bit (DN bit 13) is reset when the ACC value is equal to the PRE
value. The DN bit is set when the rung becomes true
Counters
• A counter is a simple device intended to do one simple thing-count.
Every PLC has counter instructions.

• Counters usually use low-to-high transition from an input to trigger


the counting action.

• Counters count the number of low-to-high transitions on the input line


• Similar to Timers, which count the number of time increments

• Counters also have a reset instruction to clear the accumulated count


Count-up Counter (CTU)
The CTU is an instruction that counts false-to-true rung transitions.
• Rung transitions can be caused by events occurring in the program
(from internal logic or by external devices) such as parts traveling past a detector
or actuating a limit switch.

• The ability of the counter to detect false–to–true transitions depends on the speed
(frequency) of the incoming signal.

• The accumulated value is retained when the rung conditions again become false.

• The accumulated count is retained until cleared by a reset (RES) instruction.


CTU Counter Bits
Count-Up Counter Ladder Diagram
Count-Down Counter (CTD)
• The CTD is an instruction that counts false-to-true rung transitions.
• – Rung transitions can be caused by events occurring in the program such as parts
traveling past a detector or actuating a limit switch.
• When rung conditions for a CTD instruction have made a false-to-true transition,
the accumulated value is decremented by one count, provided that the rung
containing the CTD instruction is evaluated between these transitions.
• The accumulated counts are retained when the rung conditions again become
false.
The accumulated count is retained until cleared by a reset (RES) instruction.
References
• Bolton W., “Mechatronics – Electronics Control Systems in
Mechanical and Electrical Engineering”, 4th Edition, Pearson
Education Press, 2010.

• R.K. Rajput, “A text book of Mechatronics”, 1st Edition, S. Chand and


Company Ltd., 2007.

• https://plc-coep.vlabs.ac.in/Introduction.html (Virtual Lab)

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