Chapter 9: Main Memory

INTRODUCTION TO
PAGING
• Paging is like reading a book. At any time we do not need all
pages except ones we are reading. The analogy suggest that
pages we are reading are in the main memory and the rest can
be in the secondary memory
• Logical/Virtual address space is the set of addresses that
programs use for load and store operations on disk. Logical
address space is divided into pages
• Physical address space is the set of addresses used to
reference locations in the main memory. Physical address space
is divided into frames
• Pages and frames must be of same size
• Typical page sizes range from 1KB to 64 KB. (different for
different architectures)
• Pages that have been loaded into the main memory form disk
are said to have been mapped into the main memory
• A program / process is loaded by loading its pages into available
not necessarily contiguous frames
 INTRODUCTION TO
PAGING
• To run a program having n pages, find n
free frames and load the pages into these
frames. These frames need not to be
contiguous. For example a program
comprising of 10 pages need 10 free frames
in main memory, which need not to be
contiguous. For this to work, we need to
store the mapping information of which
page is loaded in which frame, in some data
structure called “Page Table”
• No external fragmentation. Internal
Fragmentation in paging is half a page per
process
 PAGE
• Page Tables are usedTABLES
to keep
track of how logical addresses map
to physical addresses. Page table Frame
No 000
entries generally contain the frame
number where the particular page
is loaded.

• Page table size depends on the

maximum number of pages of a
process that a CPU support. E.g. if
a system support a process of
maximum 8 pages then the page
table will contain 8 rows (length is
111
debatable). So the address of
page table will consist of 3 bits
USE OF PAGE
TABLES
Frame # of memory
Page # of a process where this page is
loaded.
 LOGICAL & PHYSICAL ADDRESS FORMAT IN
PAGING
Logical Address format (p, d)

• Address generated by CPU is divided into:

– Page number (p) – used as an index into a page
table which contains base address of each page in
physical memory.
– Page offset (d) – combined with base address of
frame to define the physical memory address that
is sent to the memory unit.

Physical Address format (f, d)

• Physical address translated from the L.A is divided

into:
– Frame number (f) – kept in the page table
against the page number.
– Frame offset (d) – is the same as the page offset
 ADDRESS TRANSLATION ARCHITECTURE IN
• PAGING
Address translation means conversion of logical address
into the equivalent physical address.

Index to the page table

Displacement
within the page
 PAGING
EXAMPLE
• Page size =4
bytes
Page#
Frame#
• Process address space =
0111
• 4pages
Physical address space =
8frames
(p,d)
• Logical address: (1,3) =
0111
(f,d)
• Physical address: (6,3) = No of bits for page no = 2
11011 No of bits for frame no = 3
No of bits for offset =2

11011
 SAMPLE
PROBLEMS
Problem 1
Consider a logical address space of 64 pages of 1,024 words each,
mapped onto a physical memory of 32 frames.
a. How many bits are there in the logical address?
b. How many bits are there in the physical address?
Problem 2
Consider a logical address space of 256 pages with a 4-KB page size,
mapped onto a physical memory of 64 frames.
a. How many bits are required in the logical address?
b. How many bits are required in the physical address?
Problem 3
Assuming a 1-KB page size, what are the page numbers and offsets for
the following address references (provided as decimal numbers):
a. 3085
b. 42095
 SAMPLE
PROBLEMS
Problem 4
Consider a logical address space of 4 GB of 4 KB page size each,
mapped onto a physical memory of 512MB. How many
entries are there in each of the following?

a. How many number of pages are in logical address space?

b. How many number of frames are in physical address space?
c. How many number of entries are in page table?
d. What is the size of page table?
e. How many bits are there in the offset address?
f. How many bits are there in the logical address?
g. How many bits are there in the physical address?
IMPLEMENTATION
OF PAGE
TABLE
 IMPLEMENTATION OF PAGE TABLES
(cont…) CACHE / TLB
IN ASSOCIATIVE
• Use a Cache / Translation Look Aside Buffer (TLB)
• Place references of some of the recently used pages in TLB,
i.e. a portion of page table resides in TLB and the rest in
main memory
• On a context switch, the TLB is flushed and loaded with values for
the scheduled processes. (Normally TLB contains the page
numbers of the currently running process)
• If mapping is found page hit else page fault
 IMPLEMENTATION OF PAGE TABLE
(cont…)
PAGING
HARDWARE

LA

CPU P d
Page # Frame #
TLB
f Hit

PA
f d

TLB
TLB (Cache)
Miss
f

Physical
Memory

PT
(In main memory)
STRUCTURE
OF PAGE
TABLE
 STRUCTURE OF PAGE
TABLE day by day due to the large
• L.A space increases
size of processes, thus increasing the size of the
Page Table
• Thus there is a dire need to structure Page Table in
a better way especially in situation where the Page
Table becomes larger in size than a single page
size, i.e. a page table cannot be contained by a
single page
• We can use following techniques for the structure of
our page tables:
a.Multi level / Hierarchical Page Table
 Multi level / Hierarchical Page
Tables
• The page table is divided into smaller levels, forming a hierarchy. Instead
of storing all mappings in one large table, it uses multiple smaller tables.
• The logical address is broken into multiple parts, each used to navigate
through the hierarchy.
• Saves memory by only creating lower-level tables for pages that are
actually in use.
• If you have 1,000 pages but only use 10, the rest of the page table
doesn't take up unnecessary space.
 Inverted Page
• A Page Table has one Tables
entry for each Page in the Logical Address
space of process
• An Inverted Page Table has one entry for each Frame in the Physical
Address space (Physical Memory)
• Entries of a Page Table contains Frame numbers
• Entries of a Inverted Page Table contains Page numbers and pid
(information about the process that owns that page)
• Page Table is indexed with page number, p
• Inverted Page Table is indexed with Frame number, f
• Inverted Page Tables are used to reduce the size of page table
• Only one page table is required in the system. (All processes will have /
share a single Inverted Page Table)
• Page table size is limited by the number of frames (i.e. the physical /
main memory) and not Process Address Space
• Each entry in the Page Table contains pid and p#. There is a possibility
that there are two processes executing at a time and each process has
a page no 3. So to avoid this confusion we have to keep pid as well
• 64 bit Ultra SPARC and IBM Power PC uses this technique

1/23/2011 CMP320 Operating System 17

 Hashed Page
Tables
• Another common approach to handle address spaces larger than
32 bits

is Hashed Page Table

• Hashing. A key is given, you pass it through a function that

returns an integer value known as hash value, which is used to

index a table / array (hash value must be within that array) where

the required record will be lying or may contain a pointer to the

record (link list)

• Hash Function. A function used to manipulate the key of an

element in a

list to identify its location in the list

 Hashed Page Tables
(cont…)

• Hashing can be combined with Inverted Page Tables, to

overcome its limitation of complex / time consuming search.
• For 64 bit address space Clustered Page Tables are used.