Memory Array Organization

2D Organization
- Memory cells are organized in the form of 2D array.
- Each raw refers to a word line.
- Each column refers to a bit of word (data lines).
- Decoders are used to select rows and columns.
Example: 32K words memory uses 15X215 decoder for row selection.
Word Bit line
Word line

Address nX2n word

selection select
Lines decoder 2n words
for rows

Read/Write Column I/O circuit

Data lines
 Memory Array Organization
3D Organization
- n-bit address of rows is divided into two parts x and y.
- Each x and y contains equal or nearly equal bits
Example: In 32K words memory x and y decoders have 7 or 8 bits.

Word Bit line

Word line
x
decoder
Address
selection
Lines 2n words
for rows y
decoder

Read/Write Column I/O circuit

Data lines
 Memory Array Organization
2.5D Organization
- Column decoder is segmented
Example: 512X512 words memory uses 9 bits for row decoder and 9 bits for column decoder.

2n columns Bit line

Word line

Address nX2n word

selection select
Lines decoder 2n rows
for rows

Decoder for selection of

Read/Write Columns with I/O circuits

Bit in Bit out

 Cache Memory
Flow chart : Start

Access address from CPU

Is word(block) yes Fetch access address word(block) and

of access address Deliver it to CPU
in cache ?

no
Access main memory for word(block) containing address
generated by CPU

Allocate cache slot for main memory word(block) done

Deliver access address word(block) to CPU

Load main memory block into cache slot

 PERFORMANCE OF CACHE
Memory Access
All the memory accesses are directed first to Cache
If the word is in Cache; Access cache to provide it to CPU
If the word is not in Cache; Bring a block (or a line) including that word to replace a block now in
Cache
Performance of Cache Memory
It is measured in terms of hit ratio. Hit ratio represented by H and Miss
ratio represented by M.
M=1-H and H=N1/(N1+N2)
where N1 is number of hits (number of address references satisfied by cache) and N2 is number

of misses (number of address references satisfied by main)

i.e. Hit Ratio (H) is % of memory accesses satisfied by Cache memory system.
Ta: Average memory access time in Cache memory system MAIN MEMORY
Tc: Cache access time Tm
Tm: Main memory access time CPU
Tb: Block access or block transfer time Tb
Ta=HTc+(1-H)Tm and Tm=Tc+Tb
Ta=Tc+(1-H)Tb Tc CACHE MEMORY
But Tm >>Tc so Tm=Tb
Ta = Tc + (1 - H) Tm
Access time ratio (cache-main) r=Tm/Tc and access efficiency e=Tc/Ta
For Two-level cache Ta=H1Tc1+(1-H1)H2Tc2+(1-H1)(1-H2)Tm
Example: Tc = 0.4 s, Tm = 1.2s, H = 0.85%
Ta = 0.4 + (1 - 0.85) * 1.2 = 0.58s
 MEMORY AND CACHE MAPPING - ASSOCIATIVE MAPPLING -
The transformation of data from main memory to cache memory is known as mapping process.
Mapping Function
Specification of correspondence between main memory blocks and cache blocks

Associative mapping Direct mapping Set-associative mapping

Example :suppose main memory size is 32KX12 and cache size is 512X12.
32K means 15-bit address of main memory
Associative Mapping
Stores both address and the content (data) of the memory word.
A CPU address of 15 bits is placed in argument register.
Associative memory is searched for a matching address.
If address is found, the corresponding 12 bit data is read and sent to CPU.
The address-data pair is transferred to associative cache memory.

Note : All numbers in octal.

address (15 bits)

Argument register

Address Data
01000 3450
02777 6710
22235 1234
 MEMORY AND CACHE MAPPING - DIRECT MAPPING -
- Each memory block has only one place to load in Cache
- n-bit memory address consists of 2 parts; k bits of Index field and n-k bits of Tag field
-n-bit addresses are used to access main memory and k-bit Index is used to access the Cache
-Each word in cache consists of tag-data pair
-When CPU generates a memory request, the index field is used to access the cache

Addressing Relationships Tag(6) Index(9)

00 000 32K x 12
000
512 x 12
Main memory Cache memory
Address = 15 bits Address = 9 bits
Data = 12 bits Data = 12 bits
77 777 777

Direct Mapping Cache Organization

Memory
address Memory data
00000 1220 Cache memory
Index
address Tag Data
00777 2340 000 00 1220
01000 3450

01777 4560
02000 5670

777 02 6710
02777 6710
 DIRECT MAPPING
Operation
- CPU generates a memory request with (TAG;INDEX)
- Access Cache using INDEX ; (tag; data)
Compare TAG and tag
- If matches -> Hit
Provide Cache[INDEX](data) to CPU
- If not match -> Miss
M[tag;INDEX] <- Cache[INDEX](data)
Cache[INDEX] <- (TAG;M[TAG; INDEX])
CPU <- Cache[INDEX](data)
Disadvantage
- hit ratio drops considerably if two or more words with same index but of different tags are
accessed repeatedly

Direct Mapping with block size of 8 words

Index tag data 6 6 3
000 01 3450 Tag Block Word
Block 0
007 01 6578
010 INDEX
Block 1
017

- Index field also known as line field

- Block field is also known as slot field
Block 63 770 02 - Index implies words in cache
777 02 6710
 MEMORY AND CACHE MAPPING - SET ASSOCIATIVE MAPPING

- Each memory block has a set of locations in the Cache to load

Set Associative Mapping Cache with set size of two

Index Tag Data Tag Data
000 01 3450 02 5670

777 02 6710 00 2340

Each word of cache can store two or more words of memory with same index address.
In this example word length =2(6+12) i.e. 36bits and the size of cache memory =512X36.

Operation
- CPU generates a memory address(TAG; INDEX)
- Access Cache with INDEX, (Cache word = (tag 0, data 0); (tag 1, data 1))
- Compare TAG and tag 0 and then tag 1
- If tag i = TAG -> Hit, CPU <- data i
- If tag i  TAG -> Miss,
Replace either (tag 0, data 0) or (tag 1, data 1),
Assume (tag 0, data 0) is selected for replacement,
M[tag 0, INDEX] <- Cache[INDEX](data 0)
Cache[INDEX](tag 0, data 0) <- (TAG, M[TAG,INDEX]),
CPU <- Cache[INDEX](data 0)
 CACHE WRITE
Write Through
When writing into memory
If Hit, both Cache and memory is written in parallel
If Miss, Memory is written
For a read miss, missing block may be overloaded onto a cache block
Memory is always updated
Slow, due to the memory access time

Write-Back (Copy-Back)
When writing into memory
If Hit, only Cache is written
If Miss, missing block is brought to Cache and write into Cache
For a read miss, candidate block must be written back to the memory
Memory is not up-to-date, i.e., the same item in Cache and memory may have different value

Cache Initialization
The cache is initialized when power is applied or when main memory is loaded from auxiliary memory.
After initialization cache is considered to be empty.
Each word in cache include valid bit to indicate whether or not word contains valid data.
The cache is initialized by clearing all the valid bits to 0.
When the word is loaded from main memory, the valid bit of cache memory is set to 1.
 Problem-Cache Memory

12.15 A two-way set associative cache memory uses blocks of 4 words. The cache can accommodate a total
of 2048 words from main memory. The main memory size is 128KX32.
(a) Formulate all pertinent information required to construct the cache memory.
(b) What is the size of cache memory?
Solution :
Tag(7) Index(10)
(a) 128K means 17 bits address. The set size is 2 (given)
Hence words in cache = 2048/2 i.e. 1024 it means index size is of 10 bits. So tag size = 17-10 i.e. 7 bits
(b) The size of cache memory = 1024 * 2*(7+32)
Tag1(7) Data1(32) Tag2(7) Data2(32)

12.16 The access time of a cache memory is 100 ns and that of main memory 1000 ns. It is estimated that 80%
of memory requests are for read and the remaining 20% for write. The hit ratio for read accesses only is
0.9. A write-through procedure is used.
(a) What is the average access time of the system considering only memory read cycles?
(b) What is the average access time of the system for both read and write requests?
(c) What is the hit ratio taking into consideration the write cycles?
Solution :
(a) Access time = 0.9*100 +0.1*(1000+100) = 90 + 110 =200 ns
(b) Access time = 0.2*1000 + 0.8*200 = 200 + 160 =360 ns
(c) Hit ratio = 0.8*0.9 = 0.72
 Problem-Cache Memory
12.17 A four-way set-associative cache memory has 4 words in each set. A replacement procedure based on the
least recently used (LRU) algorithm is implemented by means of 2-bit counters associated with each word
in the set. A value in the range 0 to 3 is thus recorded for each word. When a hit occurs, the counter
associated with the referenced word is set to 0, those counters with values originally lower than the
referenced one are incremented by 1, and all other remains unchanged. If a miss occurs, the word with
counter value 3 is removed, the new word is put in its place, and its counter is set to 0. The other three
counters are incremented by 1. show that this procedure works for the following sequence of word
reference : A, B, C, D, B, E, D, A, C, E, C, E. (Start with A, B, C, D as the initial four words, with word A being
the least recently used.)
Solution : 3 2 1 0
A B C D
B is hit A C D B
E is miss C D B E
D is hit C B E D
and so on

12.18 A digital computer has a memory unit of 64KX16 and a cache memory of 1K words. The cache uses direct
mapping with a block size of 4 words.
(a) How many bits are there in the tag, index, block and word fields of the address format?
(b) How many bits are there in each word of cache and how are they divided into functions? Include a valid bit.
(c) How many blocks can the cache accommodate?
Solution :
(a) 64K means address is of 16 bits.
cache memory size 1K means index size is of 10 bits. Tag Block Word
4 words in a block means word size is of 2 bits. 6 8 2
since index = block + word hence block size is of 10 -2 i.e. 8 bits.
since tag = address – index hence tag size is of 16-10 i.e. 6 bits.
(b) Since word length is 16 hence 16 bits are there in each word i.e. data size is of 16 bits.
1 valid bit (given) V Tag Data
6 bits for tag 1 6 16

(c) Since block size is 8 bits hence total blocks = 28 i.e. 256