Module 1

Presentation 4
Architectural Classification schemes

 Three computer architectural classification

schemes are :
1. Flynn’s classification(1966)
It is based on the multiplicity of instruction
streams and data streams in a computer
system.
2. Feng’s scheme(1972)
It is based on serial versus parallel
processing
3. Handler’s classification(1977)
It is determined by the degree of parallelism
and pipelining in various subsystem levels.
1. Flynn’s classification :

 The most popular taxonomy of computer

architecture was defined by Flynn in 1966.
 Flynn’s classification scheme is based on the
notion of a stream of information
 The term stream is used here to denote a
sequence of items(instructions or data)as
executed or operated upon by a single
processor
 Two types of information flow into a processor:
instructions and data.
 An instruction stream is a sequence of
instructions as executed by the machine.
 A data stream is a sequence of data including
input, partial or temporary results ,called for, by the
instruction stream.
 M J Flynn classify the computer on the basis of
number of instruction and data items processed
simultaneously.
Classification

I. Single Instruction Stream , Single Data

Stream(SISD)
II. Single Instruction Stream ,
Multiple Data
Stream(SIMD)
III. Multiple Instruction Stream , Single
Data
Stream(MISD)
IV. Multiple Instruction Stream, Multiple
Data
Main components:

 Both instructions and data are fetched from the memory

modules.
 Instructions are decoded by the control unit, which sends the
decoded instruction stream to the processor units for
execution.
 Data streams flow between the processors and the memory
bidirectionally.
 Multiple memory modules may be used in the shared memory
subsystem. Multiple data streams originate from the
subsystem of shared memory modules
 Each instruction stream is generated by an independent
control unit.
I. Single Instruction Stream , Single Data
Stream(SISD) :

 It represents the organization containing single control

unit ,a processor unit and a memory unit. Instruction are
executed sequentially and system may or may not have
internal parallel processing capabilities.
 Single control unit (CU) fetches single Instruction Stream (IS)
from memory. The CU then generates appropriate control
signals to direct single processing element (PE) to operate on
single Data Stream (DS) i.e. one operation at a time .
 Instructions are executed sequentially but may be overlapped
in their execution stages(pipelining).
 Most SISD uniprocessor systems are pipelined. An
SISD computer may have more than one
functional unit in it. All the functional units are
under the supervision of one control unit.
Examples:
older generation mainframes, minicomputers,
workstations and single processor/core PCs.
Block Diagram:
Eg.
II. Single Instruction Stream, Multiple Data
Stream(SIMD) :

 It represents an organization that includes many

processing units under the supervision of a
common control unit.
 All PEs receive the same instruction broadcast from
the control unit but operate on different data
sets from distinct data streams.
 The shared memory subsystem may contain
multiple modules.
 Examples:
Processor Arrays: Thinking Machines CM-2 ,
MasPar MP-1 & MP-2, ILLIAC IV
Vector Pipelines: IBM 9000, Cray X-MP, Y-MP &
C90, Fujitsu VP, NEC SX-2, Hitachi S820, ETA10
Most modern computers, particularly those with
graphics processor units (GPUs) employ SIMD
instructions and execution units.
Block Diagram :
Eg.
III.Multiple Instruction Stream ,
Single Data Stream(MISD) :
 Multiple instructions operate on a single data
stream.
 Uncommon architecture which is generally used for
fault tolerance.
 Heterogeneous systems operate on the same
data stream and must agree on the result.
 Examples
the Space Shuttle flight control computer.
Block diagram :
Eg.
IV.Multiple Instruction Stream, Multiple Data
Stream(MIMD) :

 It refersto a computer system

capable of processing several programs at
the same time.
 Multiple-instruction multiple-data streams (MIMD)
parallel architectures are made of multiple
processors and multiple memory modules
connected together via some interconnection
network.
They fall into two broad categories:
shared memory or message passing.
 Processors exchange information through
their central shared memory in shared memory
systems, and exchange information through their
interconnection network in message passing
systems.
Examples:
most current supercomputers, networked
parallel computer clusters and "grids", multi-
processor SMP computers, multi-core PCs.
Block Diagram
2. Feng’s scheme(1972)

 Feng’s classification is mainly based on degree of

parallelism to classify parallel computer
architecture.
 The maximum number of binary digits that can
be process per unit time is called maximum
parallelism degree P.
 The average parallelism degree a.
 Where T is a total processor cycle
 The utilization of computer system within T cycle is
given by:
 When = it means that utilization of computer system is 100
%.
 The utilization rate depends on the application program
being executed.
 A bit slice is a string of bits, one from each of the words at
the same vertical bit position.
 The maximum parallelism degree P(C) of a given computer
system C is represented by the product of the word length
n and the bit-slice length m; that is,
 P(C)= n.m
 The pair (n,m) corresponds to a point in the computer space.
Four types of processing methods:

i. Word –serial and bit-serial(WSBS) :

has been called bit parallel processing because
one bit is processed at a time.
ii. Word –parallel and bit-serial(WPBS) :
has been called bit slice processing because m-bit
slice is processes at a time.
 iii. Word –serial and bit-parallel(WSBP) :
Is found in most existing computers and has been
called as Word Slice processing because one word
of n bit processed at a time.
 iv. Word –Parallel and bit-parallel(WPBP) :
Is known as fully parallel processing in which an
array on n x m bits is processes at one time.
Feng’s computer system
classification :
Handler’s Classification

 Handler’s proposed an elaborate notation for expressing

the pipelining and parallelism of computers. He divided
the computer at three levels.
1. Processor Control Unit(PCU)
PCU corresponds to CPU
2. Arithmetic Logic Unit(ALU)
ALU corresponds to a functional unit or PE’s in an
array processor.
3. Bit Level Circuit(BLC)
BLC corresponds to the logic needed for performing
operation in ALU.
 He uses three pairs of integers to describe computer:
ie, Computer = (k*k’, d*d , w*w’)
Where, k= no. of PCUs
k’=no. of PCUs which are pipelined
d=no. of ALUs control by each PCU
d’=no. of ALUs that can be pipelined
w=no. of bits or processing elements in ALU
w’=no. of pipeline segments
 “ * ” operation is used to show that units are
pipelined.
“ + ” operator is used to show that units are not
pipelined.
“ v ” operator is used to show that computer
hardware can work in one of the several
mode.
“ ~ ” operator is used to show that range of
any parameter
Consider the following model and observe how
handlers differentiate them on the basis of degree of
parallelism and pipelining.

1. CDC 6600
2. Cray-1
3. Illiac-IV
1. CDC 6600

 This model consist single processor which is

supported by 10 I/O processor. One control unit
control one ALU with 60 bit word length. The
ALU has 10 functional unit which are in pipelined
manner. 10 I/O processor work parallel with
each other and with CPU.
 Each I/O processor contains 12 bit ALU.
 The description for 10 I/O processor:
CDC 6600 I/O= (10, 1, 12)
 The description for main processor:
CDC 6600 main= (1, 1*10,60)
 In this model main and I/O processor are pipelined.
So that * operator will be used to combine both of
them.
CDC 6600 = (I/O processor) * (main processor)
Cray-1

 Thismodel having 64 bit single processor

computer. ALU has 12 functional unit and
8 of which are pipelined. The range of
functional units are 1 to 14.
 The description for Cray-1:
Cray-1 = (1, 12*8,(1~14))
3. Illiac-IV

 It is made up from arrays which are connected in

a mesh. The total 64 arrays have 64 bit ALUs, it
has two DEC PDP-10 as the front end. Whereas
Illiac-IV accept data from one PDP-10 at a time.
PDP-10 Illiac - IV= (2,1, 36)*(1,64,64)
 This model will also work in half word mode, at
that time it has 128 processor of 32 bit each
instead by normal 64 processor of 64 bit each.
 PDP-10 Illiac-IV/2 = (2,1,36)*(1,128,32)
 Combining this with above we get
PDP-10 Illiac-IV = (2, 1 ,36)*[(1, 64,64)v(1,128,32)]