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Pipelining Unit 3

Pipelining is a technique that allows multiple instructions to be processed simultaneously in stages, enhancing efficiency in execution. An example using laundry illustrates that pipelining reduces the total time required to complete tasks by overlapping operations. However, pipelining can encounter hazards such as structural, data, and control hazards that need to be managed for optimal performance.

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12 views19 pages

Pipelining Unit 3

Pipelining is a technique that allows multiple instructions to be processed simultaneously in stages, enhancing efficiency in execution. An example using laundry illustrates that pipelining reduces the total time required to complete tasks by overlapping operations. However, pipelining can encounter hazards such as structural, data, and control hazards that need to be managed for optimal performance.

Uploaded by

sanjaygpatel19
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Topic:

Pipelining
• A Pipelining is a series of stages, where some work is done at
each stage in parallel.
• The stages are connected one to the next to form a pipe -
instructions enter at one end, progress through the stages, and exit
at the other end.
Pipelining Case: Laundry

• 4 loads of laundry that need to


washed, dried, and folded.
– 30 minutes to wash, 40 min. to dry, and 20 min. to fold.
– We have 1 washer, 1 dryer, and 1 folding station.

• What’s the most efficient way to get the 4 loads


of laundry done?
Non Pipelined Laundry

• Takes a total of 6 hours; nothing is done in parallel


Pipelined Laundry

• Using this method, the laundry would be done at 9:30.


Definition:
Pipelining is an speed up technique where multiple
instructions are overlapped in execution on a
processor.
Pipelining: Processors

• Computers, like laundry, typically perform the exact


same
steps for every instruction:
– Fetch an instruction from memory
– Decode the instruction
– Execute the instruction
– Read memory to get input
– Write the result back to memory
Instruction
•
Pipeline
Instruction execution process lends itself naturally
to pipelining
– overlap the subtasks of instruction fetch, decode and execute

• Instruction pipeline has six operations,


⮚ Fetch instruction (FI)
⮚ Decode instruction (DI)
⮚ Calculate operands (CO)
⮚ Fetch operands (FO)
⮚ Execute instructions (EI)
⮚ Write result (WR)

Overlap these operations


CS211 8
Instructions Fetch
• The IF stage is responsible for obtaining the requested
instruction from memory. The instruction and the program
counter are stored in the register as temporary storage.

CS211 9
Decode Instruction
• The DI stage is responsible for decoding the instruction
and sending out the various control lines to the other
parts of the processor.

CS211 10
Calculate Operands
• The CO stage is where any calculations are performed.
The main component in this stage is the ALU. The
ALU is made up of arithmetic, logic and capabilities.

CS211 11
Fetch Operands and Execute Instruction
• The FO and EI stages are responsible for storing and
loading values to and from memory. They also responsible
for input and output from the processor respectively.

CS211 12
Write Operands
• The WO stage is responsible for writing
the result of a calculation, memory access or input
into the register file.

CS211 13
Six Stage
Instruction
Pipeline
Timing Diagram for
Instruction Pipeline
Operation
6
Pipeline Performance: Clock &
Timing
Si S
i+1

τ τm d

Clock cycle of the pipeline : τ

Latch delay : d
τ = max {τm
}+d

Pipeline frequency : f
CS211 16
7
Pipeline Performance: Speedup & Efficiency

k-stage pipeline processes n tasks in


k + (n-1) clock cycles:

k cycles for the first task and n-1


cycles for the remaining n-1 tasks

Total time to process n tasks

Tk = [ k + (n-1)] τ

For the non-pipelined processor

T1 = n k τ

Speedup factor T1 nk nk
Sk = τ =
Tk [k
+ (n-1)] τ k + (n-1)
= CS211 17
Advantages

• Pipelining makes efficient use of


resources.
• Quicker time of execution of large
number of instructions
• The parallelism is invisible to the
programmer.
Can Pipelining Get Us Into Trouble?
❑ Yes: Pipeline Hazards
● structural hazards: attempt to use the same resource by
two different instructions at the same time
● data hazards: attempt to use data before it is ready
- An instruction’s source operand(s) are produced by a prior
instruction still in the pipeline
● control hazards: attempt to make a decision about program
control flow before the condition has been evaluated and
the new PC target address calculated
- branch instructions

❑ Can always resolve hazards by waiting


● pipeline control must detect the hazard
● and take action to resolve hazards

CSE431 L06 Basic MIPS Pipelining.19 Irwin, PSU, 2005

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