Unit 2

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 Differential pair with MOS Loads

• The implementation of differential pair need not to be linear resistors

• It employs diode – connected or current source load
• The implementation of differential pair need not to be linear resistor
• It employs diode-connected or current source load
• Small signal differential gain--
-----------(1)
-----------(2)
• Where, N- Nmos
• P- Pmos

--------(3)

-------(4)

Differential Amplifiers
Ch. 4 # 3
• In fig the diode connected load consume voltage
• Therefore creates trade-offs b/w o/p voltage swings, voltage gain, i/p
CM range.
• To achieve high gain
• (W/L)p  decrease
•  increasing

• CM level at node x & y  lowering

• In fig 2, the main idea – lower the gm of load devices
• by reducing their current
• Ex: if M5 & M6 carry 80 percent of drain current of M1 & M2
• The current through M3 & M4 is reduced by factor of 5
• For a given
• This translates to a factor of 5
 Reduction in transconductance of M3
 Because the accept ratio can be lowered by same factor
I.e 5
 Therefore differential gain is approximately 5 times that
of the case with no pmos current sources
 To increase the o/p impedance of pmos & nmos
cascoding is done.
 To create a differential version of cascode stage fig 3.a
Differential Amplifiers
Ch. 4 # 5
 MOS Loads (cont.)

Av  g m1[( g m 3 ro 3 ro1 ) || ( g m 5 ro 5 ro 7 )]     (5)

 Gilbert Cell

• The differential pair reveals 2 important ascepts:

• 1)small signal gain is a function of tail current
• 2)2 transistors in a differential pair provide a simple means of
steering the current one of the 2 destinations
• By combining these 2 properties,
• Develop a versatile building block.

Differential Amplifiers
Ch. 4 # 7
Gilbert Cell
• In fig 1.a construct a differential pair
• Gain is varied by control voltage  defines the tail current & hence
the gain
• In this topology,
• varies from 0 to max voltage
• This circuit is a simple example of a “variable gain amplifier” VGA

• In fig b: amplifier whose gain can be continuously varied from –ve

value to a +ve value
• Consider 2 differential pair that amplify the input by output gains

Differential Amplifiers
Ch. 4 # 9
Gilbert Cell (cont.)
Gilbert Cell (cont.)
• In fig 2. a, if Vout1 & Vout2 is combined into single o/p
• The 2 v/g can be summed, producing

• The actual implementation is

• So that

Differential Amplifiers
Ch. 4 # 12
• In fig 2.b: add Vout1 & Vout2
• Short the corresponding drain terminals to sum the current
• & generate the output voltage.
• If = 0
• Then

• In fig 2.c: circuit can vary 2 current in opposite directions

• For large
• All the tail current is steered to one of the top differential pair
• Gain from Vin & Vout is at most +ve or most –ve
• For

Differential Amplifiers
Ch. 4 # 13
• In fig 2.d: redraw the circuit called “gilbert cell”
• As a cascode structure,
• Gilbert cell consumes  high voltage
• Because 2 differential pair M1 – M2 & M3 – M4 are “stacked” on
the top of control differential pair
• Suppose differential input Vin in fig 2 d. has common mode level
Vcm,in

• For M5 & M6 operates in saturation

Differential Amplifiers
Ch. 4 # 14
Gilbert Cell (cont.)
• In gilbert cell topology,
• In fig 3,a:
• To vary gain of each differential pair,
• There by applying control voltage to bottom pair & input signals to
top pairs.
• The idea is to convert input voltage to current by M5 & M6
• & route the current through M1 & M4 to the o/p nodes

• In fig 3.b
• Vcont  +ve
• M1& M2 are on

Differential Amplifiers
Ch. 4 # 16
• In fig 3.c
• Vcont = -ve
• M3 & M4 are on

• If differential control voltage 0

• Vout  0
• The input differential pair incorporate degeneration to provide a
linear voltage to current conversion

Differential Amplifiers
Ch. 4 # 17
Copyright © The McGraw-Hill
Companies, Inc. Permission
required for reproduction or
Differential Amplifiers
display. Slides prepared by
Ch. 4 # 18
Travis N. Blalock, University
Copyright © The McGraw-Hill
Companies, Inc. Permission
required for reproduction or
Differential Amplifiers
display. Slides prepared by
Ch. 4 # 19
Travis N. Blalock, University
Copyright © The McGraw-Hill
Companies, Inc. Permission
required for reproduction or
Differential Amplifiers
display. Slides prepared by
Ch. 4 # 20
Travis N. Blalock, University
 Unit2 Chapter2
Passive and Active Current Mirrors

Current Mirrors
Ch. 2 # 2
• This chapter deals with design of current mirrors as bias elements &
signal processing components.

Current Mirrors
Ch. 5 # 22
Basic current mirrors

Current Mirrors
Ch. 5 # 23
 • Fig illustrates where a current source
proves useful.
• This fig consider the simple resistor
biasing assuming m1 is in saturation.

un Cox W R2 2
IOUT  ( VDD  VTH )
2 L R2  R1
• This expression reveals varies dependencies of Iout upon the supply,
process & temperature.
• The overdrive v/g is a function of Vdd & Vth.
• The threshold v/g varies by 100mV.
•  exhibits temperature dependencies
• Therefore Iout is poorly defined.
• Note: the process & temperature dependencies  exist if gate v/g is
not a function of supply v/g
• Ie., if gate- source v/g of the mosfet  is precisely defined
• Then drain current is not equal.

• So to design, current source in analog circuits is based on “coping”

current from reference.

Current Mirrors
Ch. 5 # 25
• In complex circuit  sometimes requiring external adjustments
• It is used to generate a stable reference current Iref
• Which is copied to many current sources in the system

Current Mirrors
Ch. 5 # 26
• For a mosfet,
• Denotes function of Id v/s Vgs
• Then
• Now if a transistor is biased at Iref

Current Mirrors
Ch. 5 # 27
• In fig b, the structure consisting of M1 & M2 is called “current mirror”
• The device need not to be identical.
• Neglecting channel length modulation,

Current Mirrors
Ch. 5 # 28
Amplifier Bias Example

Current Mirrors
Ch. 5 # 29
• Here differential pair is biased by means of an Nmos mirror for the
tail current source.
• & a Pmos mirror for load current source.
• Device dimension of drain current =
• Then drain current of M3 & M4  reduces
• Gain  increases.
• In fig 5.7. the Nmos current source must have same channel length
as M0 because is doubled.

• Threshold v/g of short channel device exhibits some dependence on

channel length
• In fig 5.5 b,
• Then

Current Mirrors
Ch. 5 # 30
 Cascode Current Mirror
• Till now, we have neglected channel length modulation
• The effects of the results in significant errors in coping currents

Current Mirrors
Ch. 5 # 31
Cascode Current Mirror

Current Mirrors
Ch. 5 # 32
• Fig 5.9 a,: if Vb is chosen such that Vy=Vx
• Then Iout closely tracks Iref
• The cascode devide “shields” the bottom transistors from variations in
Vp
• W.K.T
• Therefore Vy remains close to Vx
• Hence
• Accuracy  high

• To generate Vb, ensure Vy=Vx

• This result suggests that,

• If gate- source v/g is added to Vx,
• Then Vb is obtained.

Current Mirrors
Ch. 5 # 33
• In fig 5.9b, place another diode M0 in series with M1
• Therefore generating a v/g
• Proper choice of dimensions of M0 w.r.t M3  yields

• In fig 5.9 c, connect the node N to M3

• Then
• If
• Then
•

Current Mirrors
Ch. 5 # 34
Cascode Current Mirror (cont.)

Current Mirrors
Ch. 5 # 35
• In fig 5.11(a): Vb is chosen to allow the lowest possible value of Vp
• But o/p current doesn’t accurately track Iref
• Because M1 & M2 sustain unequal drain-source v/g

• In fig 5.11(b): accuracy  high

• But minimum level at P is high by 1 threshold v/g

Current Mirrors
Ch. 5 # 36
• Fig 5.13 a, this circuit cascode topology with o/p shorted to its i/p
• We must have for M2 to be saturated

• In fig 5.13.b: all transistors are in saturation and proper ratioing

• The cascode current source M3 & M4 consumes minimum headroom

• While M1 & M2 sustain equal drain source
• Therefore accurate coping of Iref
• This is called “low v/g cascode”
Current Mirrors
Ch. 5 # 37
Cascode Current Mirror Biasing

Current Mirrors
Ch. 5 # 38
• In fig 5.14b, here diode-connected transistor M7  has large W/L
• So

• Hence

• We requiring no resistor, this circuit suffers from similar error due to

body effect

Current Mirrors
Ch. 5 # 39
Active Current Mirrors
• It is the basic pmos circuit which acts
as current mirror
• M1 & M2 are identical
• Whatever the current flowing across
Iin will reflect across Iout
• Current through Iout is given some
active component signal
• Current mirrors can also process
signals Operate as “active elements”
• So it is called as “active current
mirrors”

Current Mirrors
Ch. 5 # 40
Active Current Mirrors (Cont…..

Current Mirrors
Ch. 5 # 41
• In fig5.17 a, consider differential pair  M1 & M2
• M3 & M4 current source load.

• In fig 5.17,b:

• In fig 5.17,c: now we have to compute Rout

• M2 is degenerated by the source output impedance
• That is the circuit is similar to common source amplifier with
regenerative circuit
• output impedance equal to

Current Mirrors
Ch. 5 # 42
• We calculate

Current Mirrors
Ch. 5 # 43
Current Mirrors
Ch. 5 # 44
Active Current Mirrors (Cont…..

Current Mirrors
Ch. 5 # 45
Active Current Mirror (Cont…

Current Mirrors
Ch. 5 # 46
 Large Signal Analysis
• In fig replace ideal tail current source
 by mosfet
• If Vin1 is much –ve than Vin2
• M1, M3, M4 off
• Since no current flows from Vdd
• M2 & M5  deep triode region
•  carrying 0 current
• Thus Vout=0
• As Vin1 approaches Vin2
• M1on (drawing part of Id5 from
M3)
• Therefore M4 on
• o/p v/g depends on diff b/w Id4 & Id2.
Current Mirrors
Ch. 5 # 47
• As Vin becomes more +ve than Vin2
• Id1, Id3, Id4 increases
• If Id2  decreases
• Then M4  triode region (0)

• If Vin1 – Vin2 is sufficiently large

• M2  off
• M4 deep triode region with 0 current
• Vout= Vdd

• Then M1 enters triode region

Current Mirrors
Ch. 5 # 48
• For M2 to be in saturation?
• o/p v/g cannot be less than
• To allow maximum o/p swings, the i/p
CM level must be low.
• I.e..  min

• When Vin1=Vin2? Or with perfect

symmetry?

• Suppose Due to C.L.M 

 M1 carry greater current thane M2
 M4 carry greater current than M3

Current Mirrors
Ch. 5 # 49
 Small-Signal Analysis

• It has small inputs

• v/g swings at node x &y are different
• Because the diode-connected device
M3 yields much lower v/g gain from
the i/p to node x

• As a result, the effects of Vx &Vy at node P do not cancel each other

• This node cannot be considered as virtual ground
• We compute the gain using 2 approaches

Current Mirrors
Ch. 5 # 50
 Small-Signal Analysis 1st approach
Calculation of Gm

• Consider the circuit is not quite symmetric

• Node P can be approximately by a virtual ground
I D1 I D 3 I D 4  g m1, 2Vin / 2 I D 2  g m1, 2Vin / 2
Iout I D2  I D4  gm1,2 Vin , Gm gm1, 2 Current Mirrors
Ch. 5 # 51
• The active mirror operation yields a different value
• Because when a v/g is applied to the o/p to measure Rout
• The gate v/g of M4 does not remain constant
• Rather than draw the entire equivalent circuit

Current Mirrors
Ch. 5 # 52
• For small signals Iss is open,
• That is any current flowing into M1 must flow out of M2
• It can be represented

VX VX
IX 2 
2ro1, 2 1/ gm 3 ro4

Rout ro2 || ro4 , (2ro1,2  [1/ gm 3 ] || ro3 )

Av gm 1,2 (ro2 || ro4 )

Current Mirrors
Ch. 5 # 53
Small-Signal Analysis 2 approach
nd

Current Mirrors
Ch. 5 # 54
Small-Signal Analysis (Cont….

Current Mirrors
Ch. 5 # 55
Small-Signal Analysis (Cont…

Current Mirrors
Ch. 5 # 56
Common Mode Characteristics

• Change in the i/p cm level leads to

change in bias current of all
transistors

Vout
ACM 
Vin,CM

Current Mirrors
Ch. 5 # 57
Common Mode (cont.)

• Here F & X are shorted that is Vin,cm increases

• Vf and Vout  drops

1 ro3,4
 ||
2 gm3,4 2 1 gm1,2
ACM  1 
 RSS 1  2 gm1,2 RSS gm 3, 4
2 gm1,2 Current Mirrors
Ch. 5 # 58
Common Mode (cont.)
ADM
CMRR 
ACM

gm 3,4 (1  2gm1,2 RSS )

gm1, 2 (ro1,2 || ro3,4 )
gm1,2

gm 3,4 (ro1, 2 || ro3,4 )(1  2gm1, 2 RSS )

Current Mirrors
Ch. 5 # 59
Common Mode (cont.) effect of mismatch

Current Mirrors
Ch. 5 # 60
Calculating current individually

Current Mirrors
Ch. 5 # 61
Common Mode (cont.)

Current Mirrors
Ch. 5 # 62
Copyright © The McGraw-Hill
Companies, Inc. Permission
required for reproduction or
Differential Amplifiers
display. Slides prepared by
Ch. 4 # 63
Travis N. Blalock, University