15-213

“The course that gives CMU its Zip!”

The Memory Hierarchy

October 5, 2004
Topics
 Storage technologies and trends
 Locality of reference
 Caching in the memory hierarchy

class11.ppt
Random-Access Memory (RAM)
Key features
 RAM is traditionally packaged as a chip.
 Basic storage unit is normally a cell (one bit per cell).
 Multiple RAM chips form a memory.
Static RAM (SRAM)
 Each cell stores a bit with a four or six-transistor circuit.
 Retains value indefinitely, as long as it is kept powered.
 Relatively insensitive to electrical noise (EMI), radiation, etc.
 Faster and more expensive than DRAM.
Dynamic RAM (DRAM)
 Each cell stores bit with a capacitor. One transistor is used for access
 Value must be refreshed every 10-100 ms.
 More sensitive to disturbances (EMI, radiation,…) than SRAM.
 Slower and cheaper than SRAM.
–2– 15-213, F’04
SRAM vs DRAM Summary

Tran. Access Needs Needs

per bit time refresh? EDC? Cost Applications

SRAM 4 or 6 1X No Maybe 100x cache memories

DRAM 1 10X Yes Yes 1X Main memories,

frame buffers

–3– 15-213, F’04

Conventional DRAM Organization
d x w DRAM:
 dw total bits organized as d supercells of size w bits

16 x 8 DRAM chip
cols
0 1 2 3
2 bits 0
/
addr
1
rows
memory supercell
2
controller (2,1)
(to CPU)
3
8 bits
/
data

–4– internal row buffer 15-213, F’04

Reading DRAM Supercell (2,1)
Step 1(a): Row access strobe (RAS) selects row 2.
Step 1(b): Row 2 copied from DRAM array to row buffer.
16 x 8 DRAM chip
cols
0 1 2 3
RAS = 2
2
/ 0
addr
1
rows
memory
controller 2

8 3
/
data

–5– internal row buffer 15-213, F’04

Reading DRAM Supercell (2,1)
Step 2(a): Column access strobe (CAS) selects column 1.
Step 2(b): Supercell (2,1) copied from buffer to data lines,
and eventually back to the CPU.
16 x 8 DRAM chip
cols
0 1 2 3
CAS = 1
2
/ 0
To CPU addr
1
rows
memory
controller 2

supercell 3
8
(2,1) /
data

supercell
–6– internal row buffer 15-213, F’04
(2,1)
Memory Modules
addr (row = i, col = j)
: supercell (i,j)
DRAM 0
64 MB
memory module
consisting of
DRAM 7
eight 8Mx8 DRAMs

bits bits bits bits bits bits bits bits

56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
Memory
controller
64-bit doubleword at main memory address A

64-bit doubleword
–7– 15-213, F’04
Enhanced DRAMs
DRAM Cores with better interface logic and faster I/O :
 Synchronous DRAM (SDRAM)
Uses a conventional clock signal instead of asynchronous control
 Double data-rate synchronous DRAM (DDR SDRAM)
Double edge clocking sends two bits per cycle per pin
 RamBus™ DRAM (RDRAM)
Uses faster signaling over fewer wires (source directed clocking)
with a Transaction oriented interface protocol

Obsolete Technologies :
 Fast page mode DRAM (FPM DRAM)
Allowed re-use of row-addresses
 Extended data out DRAM (EDO DRAM)
Enhanced FPM DRAM with more closely spaced CAS signals.
 Video RAM (VRAM)
Dual ported FPM DRAM with a second, concurrent, serial interface
 Extra functionality DRAMS (CDRAM, GDRAM)
Added SRAM (CDRAM) and support for graphics operations (GDRAM)
–8– 15-213, F’04
Nonvolatile Memories
DRAM and SRAM are volatile memories
 Lose information if powered off.
Nonvolatile memories retain value even if powered off
 Read-only memory (ROM): programmed during production
 Magnetic RAM (MRAM): stores bit magnetically (in development)
 Ferro-electric RAM (FERAM): uses a ferro-electric dielectric
 Programmable ROM (PROM): can be programmed once
 Eraseable PROM (EPROM): can be bulk erased (UV, X-Ray)
 Electrically eraseable PROM (EEPROM): electronic erase capability
 Flash memory: EEPROMs with partial (sector) erase capability
Uses for Nonvolatile Memories
 Firmware programs stored in a ROM (BIOS, controllers for disks,
network cards, graphics accelerators, security subsystems,…)
 Solid state disks (flash cards, memory sticks, etc.)
 Smart cards, embedded systems, appliances
 Disk caches
–9– 15-213, F’04
 Traditional Bus Structure Connecting

CPU and Memory

A bus is a collection of parallel wires that carry
address, data, and control signals.
Buses are typically shared by multiple devices.

CPU chip

register file

ALU

system bus memory bus

I/O main
bus interface
bridge memory

– 10 – 15-213, F’04
 Memory Read Transaction (1)
CPU places address A on the memory bus.

register file Load operation: movl A, %eax

ALU
%eax

main memory
I/O bridge 0
A
bus interface x A

– 11 – 15-213, F’04
 Memory Read Transaction (2)
Main memory reads A from the memory bus, retrieves
word x, and places it on the bus.

register file
Load operation: movl A, %eax

ALU
%eax

main memory
I/O bridge x 0

bus interface x A

– 12 – 15-213, F’04
 Memory Read Transaction (3)
CPU read word x from the bus and copies it into
register %eax.

register file Load operation: movl A, %eax

ALU
%eax x

main memory
I/O bridge 0

bus interface x A

– 13 – 15-213, F’04
 Memory Write Transaction (1)
CPU places address A on bus. Main memory reads it
and waits for the corresponding data word to arrive.

register file Store operation: movl %eax, A

ALU
%eax y

main memory
I/O bridge 0
A
bus interface A

– 14 – 15-213, F’04
 Memory Write Transaction (2)
CPU places data word y on the bus.

register file Store operation: movl %eax, A

ALU
%eax y

main memory
I/O bridge 0
y
bus interface A

– 15 – 15-213, F’04
 Memory Write Transaction (3)
Main memory reads data word y from the bus and
stores it at address A.

register file
Store operation: movl %eax, A

ALU
%eax y

main memory
I/O bridge 0

bus interface y A

– 16 – 15-213, F’04
 Memory Subsystem Trends
Observation: A DRAM chip has an access time of about
50ns. Traditional systems may need 3x longer to get
the data from memory into a CPU register.
 Modern systems integrate the memory controller
onto the CPU chip: Latency matters!
 DRAM and SRAM densities increase and so does the
soft-error rate:
 Traditional error detection & correction (EDC) is a must have
(64bit of data plus 8bits of redundancy allow any 1 bit error
to be corrected and any 2 bit error is guaranteed to be
detected)
 EDC is increasingly needed for SRAMs too
 ChipKill™ capability (can correct all bits supplied by one
failing memory chip) will become standard soon

– 17 – 15-213, F’04
 Disk Geometry
Disks consist of platters, each with two surfaces.
Each surface consists of concentric rings called tracks.
Each track consists of sectors separated by gaps.
tracks
surface
track k gaps

spindle

sectors
– 18 – 15-213, F’04
 Disk Geometry (Muliple-Platter View)
Aligned tracks form a cylinder.
cylinder k

surface 0
platter 0
surface 1
surface 2
platter 1
surface 3
surface 4
platter 2
surface 5

spindle

– 19 – 15-213, F’04
 Disk Capacity
Capacity: maximum number of bits that can be stored.
 Vendors express capacity in units of gigabytes (GB), where
1 GB = 109 Bytes (Lawsuit pending! Claims deceptive advertising).
Capacity is determined by these technology factors:
 Recording density (bits/in): number of bits that can be squeezed
into a 1 inch segment of a track.
 Track density (tracks/in): number of tracks that can be squeezed
into a 1 inch radial segment.
 Areal density (bits/in2): product of recording and track density.
Modern disks partition tracks into disjoint subsets called
recording zones
 Each track in a zone has the same number of sectors, determined
by the circumference of innermost track.
 Each zone has a different number of sectors/track

– 20 – 15-213, F’04
 Computing Disk Capacity
Capacity = (# bytes/sector) x (avg. # sectors/track) x
(# tracks/surface) x (# surfaces/platter) x
(# platters/disk)
Example:
 512 bytes/sector
 300 sectors/track (on average)
 20,000 tracks/surface
 2 surfaces/platter
 5 platters/disk

Capacity = 512 x 300 x 20000 x 2 x 5

= 30,720,000,000
= 30.72 GB
– 21 – 15-213, F’04
 Disk Operation (Single-Platter View)

The disk
The read/write head
surface
is attached to the end
spins at a fixed
of the arm and flies over
rotational rate
the disk surface on
a thin cushion of air.

spindle
spindle
spindle
spindle

By moving radially, the arm

can position the read/write
head over any track.

– 22 – 15-213, F’04
 Disk Operation (Multi-Platter View)
read/write heads
move in unison
from cylinder to cylinder

arm

spindle

– 23 – 15-213, F’04
 Disk Access Time
Average time to access some target sector approximated by :
 Taccess = Tavg seek + Tavg rotation + Tavg transfer
Seek time (Tavg seek)
 Time to position heads over cylinder containing target sector.
 Typical Tavg seek = 9 ms
Rotational latency (Tavg rotation)
 Time waiting for first bit of target sector to pass under r/w head.
 Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min
Transfer time (Tavg transfer)
 Time to read the bits in the target sector.
 Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.

– 24 – 15-213, F’04
 Disk Access Time Example
Given:
 Rotational rate = 7,200 RPM
 Average seek time = 9 ms.
 Avg # sectors/track = 400.
Derived:
 Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms.
 Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec =
0.02 ms
 Taccess = 9 ms + 4 ms + 0.02 ms
Important points:
 Access time dominated by seek time and rotational latency.
 First bit in a sector is the most expensive, the rest are free.
 SRAM access time is about 4 ns/doubleword, DRAM about 60 ns
 Disk is about 40,000 times slower than SRAM,
 2,500 times slower then DRAM.
– 25 – 15-213, F’04
 Logical Disk Blocks
Modern disks present a simpler abstract view of the
complex sector geometry:
 The set of available sectors is modeled as a sequence of b-
sized logical blocks (0, 1, 2, ...)
Mapping between logical blocks and actual (physical)
sectors
 Maintained by hardware/firmware device called disk
controller.
 Converts requests for logical blocks into
(surface,track,sector) triples.
Allows controller to set aside spare cylinders for each
zone.
 Accounts for the difference in “formatted capacity” and
“maximum capacity”.

– 26 – 15-213, F’04
 I/O Bus
CPU chip
register file

ALU
system bus memory bus

I/O main
bus interface
bridge memory

I/O bus Expansion slots for

other devices such
USB graphics disk as network adapters.
controller adapter controller

mouse keyboard monitor

– 27 –
disk 15-213, F’04
 Reading a Disk Sector (1)
CPU chip
CPU initiates a disk read by writing a
register file
command, logical block number, and
destination memory address to a port
ALU
(address) associated with disk controller.

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
– 28 – 15-213, F’04
 Reading a Disk Sector (2)
CPU chip
Disk controller reads the sector and
register file
performs a direct memory access (DMA)
transfer into main memory.
ALU

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
– 29 – 15-213, F’04
 Reading a Disk Sector (3)
CPU chip
When the DMA transfer completes, the
register file
disk controller notifies the CPU with an
interrupt (i.e., asserts a special “interrupt”
ALU
pin on the CPU)

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
– 30 – 15-213, F’04
 Storage Trends
metric 1980 1985 1990 1995 2000 2000:1980

SRAM $/MB 19,200 2,900 320 256 100 190

access (ns) 300 150 35 15 2 100

metric 1980 1985 1990 1995 2000 2000:1980

DRAM $/MB 8,000 880 100 30 1 8,000

access (ns) 375 200 100 70 60 6
typical size(MB) 0.064 0.256 4 16 64 1,000

metric 1980 1985 1990 1995 2000 2000:1980

$/MB 500 100 8 0.30 0.05 10,000

Disk access (ms) 87 75 28 10 8 11
typical size(MB) 1 10 160 1,000 9,000 9,000

– 31 – (Culled from back issues of Byte and PC Magazine) 15-213, F’04

 CPU Clock Rates

1980 1985 1990 1995 2000 2000:1980

processor 8080 286 386 Pent P-III
clock rate(MHz) 1 6 20 150 750 750
cycle time(ns) 1,000 166 50 6 1.6 750

– 32 – 15-213, F’04
 The CPU-Memory Gap
The gap widens between DRAM, disk, and CPU speeds.
See “Hitting the Memory Wall: Implications of the Obvious”,
W. A. Wulf, S. A. McKee, Computer Architecture News 1995.

100,000,000
10,000,000
1,000,000
100,000 Disk seek time
DRAM access time
10,000
ns

SRAM access time

1,000
CPU cycle time
100
10
1
1980 1985 1990 1995 2000
year

– 33 – 15-213, F’04
 Locality
Principle of Locality:
 Programs tend to reuse data and instructions near those
they have used recently, or that were recently referenced
themselves.
 Temporal locality: Recently referenced items are likely to be
referenced in the near future.
 Spatial locality: Items with nearby addresses tend to be
referenced close together in time.

Locality Example: sum = 0;

for (i = 0; i < n; i++)
• Data
sum += a[i];
– Reference array elements in succession return sum;
(stride-1 reference pattern): Spatial locality
– Reference sum each iteration: Temporal locality
• Instructions
– Reference instructions in sequence: Spatial locality
– Cycle through loop repeatedly: Temporal locality
– 34 – 15-213, F’04
 Locality Example
Claim: Being able to look at code and get a qualitative
sense of its locality is a key skill for a professional
programmer.

Question: Does this function have good locality?

int sum_array_rows(int a[M][N])

{
int i, j, sum = 0;

for (i = 0; i < M; i++)

for (j = 0; j < N; j++)
sum += a[i][j];
return sum;
}
– 35 – 15-213, F’04
 Locality Example
Question: Does this function have good locality?

int sum_array_cols(int a[M][N])

{
int i, j, sum = 0;

for (j = 0; j < N; j++)

for (i = 0; i < M; i++)
sum += a[i][j];
return sum;
}

– 36 – 15-213, F’04
 Locality Example
Question: Can you permute the loops so that the
function scans the 3-d array a[] with a stride-1
reference pattern (and thus has good spatial
locality)?

int sum_array_3d(int a[M][N][N])

{
int i, j, k, sum = 0;

for (i = 0; i < M; i++)

for (j = 0; j < N; j++)
for (k = 0; k < N; k++)
sum += a[k][i][j];
return sum;
}

– 37 – 15-213, F’04
 Memory Hierarchies
Some fundamental and enduring properties of
hardware and software:
 Fast storage technologies cost more per byte, have less
capacity, and require more power (heat!).
 The gap between CPU and main memory speed is widening.
 Well-written programs tend to exhibit good locality.

These fundamental properties complement each other

beautifully.

They suggest an approach for organizing memory and

storage systems known as a memory hierarchy.
– 38 – 15-213, F’04
 An Example Memory Hierarchy
Smaller, L0:
faster, registers CPU registers hold words retrieved
and from L1 cache.
costlier L1: on-chip L1
(per byte) cache (SRAM) L1 cache holds cache lines
retrieved from the L2 cache
storage memory.
devices L2: off-chip L2
cache (SRAM) L2 cache holds cache lines
retrieved from main memory.

L3: main memory

Larger, (DRAM)
Main memory holds disk
slower, blocks retrieved from local
and disks.
cheaper local secondary storage
L4:
(per byte) (local disks)
storage Local disks hold files
retrieved from disks on
devices
remote network servers.

L5: remote secondary storage

(tapes, distributed file systems, Web servers)

– 39 – 15-213, F’04
 Caches
Cache: A smaller, faster storage device that acts as a
staging area for a subset of the data in a larger,
slower device.
Fundamental idea of a memory hierarchy:
 For each k, the faster, smaller device at level k serves as a
cache for the larger, slower device at level k+1.
Why do memory hierarchies work?
 Programs tend to access the data at level k more often than
they access the data at level k+1.
 Thus, the storage at level k+1 can be slower, and thus larger
and cheaper per bit.
 Net effect: A large pool of memory that costs as much as
the cheap storage near the bottom, but that serves data to
programs at the rate of the fast storage near the top.

– 40 – 15-213, F’04
 Caching in a Memory Hierarchy
Smaller, faster, more expensive
Level k: 8
4 9 14
10 3 device at level k caches a
subset of the blocks from level k+1

Data is copied between

10
4 levels in block-sized transfer
units

0 1 2 3

4 5 6 7 Larger, slower, cheaper storage

Level k+1:
device at level k+1 is partitioned
8 9 10 11 into blocks.

12 13 14 15

– 41 – 15-213, F’04
 General Caching Concepts
Program needs object d, which is stored
Request in some block b.
14
12
12
14
0 1 2 3 Cache hit
Level 
4*
12 9 14 3 Program finds b in the cache at level
k:
k. E.g., block 14.

12
4* Request Cache miss
12  b is not at level k, so level k cache
must fetch it from level k+1.
E.g., block 12.
0 1 2 3  If level k cache is full, then some
Level 4
4* 5 6 7 current block must be replaced
k+1: (evicted). Which one is the “victim”?
8 9 10 11
 Placement policy: where can the new
12 13 14 15 block go? E.g., b mod 4
 Replacement policy: which block
should be evicted? E.g., LRU

– 42 – 15-213, F’04
 General Caching Concepts
Types of cache misses:
 Cold (compulsory) miss
 Cold misses occur because the cache is empty.
 Conflict miss
 Most caches limit blocks at level k+1 to a small subset
(sometimes a singleton) of the block positions at level k.
 E.g. Block i at level k+1 must be placed in block (i mod 4) at
level k+1.
 Conflict misses occur when the level k cache is large enough,
but multiple data objects all map to the same level k block.
 E.g. Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every time.
 Capacity miss
 Occurs when the set of active cache blocks (working set) is
larger than the cache.

– 43 – 15-213, F’04
 Examples of Caching in the Hierarchy
Cache Type What is Where is it Latency Managed
Cached? Cached? (cycles) By
Registers 4-byte words CPU core 0 Compiler
TLB Address On-Chip TLB 0 Hardware
translations
L1 cache 64-bytes block On-Chip L1 1 Hardware
L2 cache 64-bytes block Off-Chip L2 10 Hardware
Virtual 4-KB page Main memory 100 Hardware+
Memory OS
Buffer cache Parts of files Main memory 100 OS
Network buffer Parts of files Local disk 10,000,000 AFS/NFS
cache client
Browser cache Web pages Local disk 10,000,000 Web
browser
Web cache Web pages Remote server 1,000,000,000 Web proxy
disks server

– 44 – 15-213, F’04
 Summary
 The memory hierarchy is fundamental consequence
of maintaining the random access memory
abstraction and practical limits on cost and power
consumption.
 Caching works!
 Programming for good temporal and spatial locality
is critical for high performance.
 Trend: the speed gap between CPU, memory and
mass storage continues to widen, thus leading
towards deeper hierarchies.
 Consequence: maintaining locality becomes even more
important.

– 45 – 15-213, F’04