Computer Organization

Dr. Sulochana Sooriyaarachchi

Terminology
Blueprint/plan that is visible to programmer
Computer Key functional units, their interconnection, & instruction to program

Architecture Instruction Set Architecture (ISA)

e.g., x86 vs. ARM

Internal details of operational units, their interconnection, & control

Computer View of a computer designer
How to support multiplication – multiply circuit or repeated addition
Organization
e.g., Intel & AMD both support x86 with different organizations

Maps a given organization to a logic design, logic design to a Silicon layout, & chip
packaging
Computer View of hardware designer

Design Design decisions based on constrains like circuit-level delays, Silicon real estate,
heat generation, & cost
e.g., Intel Core i7-6800K vs. Xeon E5-2643 v4 2
What is Computer Organization?
• Organization of a Computer is defined by:
• Internal Registers
• Timing and control structures
• Set of Instructions
• Internal Organization of Digital System
• Sequence of micro-operations performed on data stored in registers
• Sequence is instructed by user as program
High-Level View of a Computer

• CPU – execute instructions

• Memory – store program & data
• IO devices – receive inputs & produce outputs
• Bus – interconnects everything by transferring data
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2nd-Level View of a Computer

5
 3rd-Level View of a
Computer

RAM &
Data IO
Program Accumulator Registers
Memory Instruction
Register

ALU
Instruction
STACK Program Counter Decoder IO
FLAG &
Special
Purpose
Registers

Timing, Control, & Register selection

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Source: Makis Malliris & Sabir Ghauri, UWE
Blocks of a Microprocessor (Cont.)
Program Execution Section Register Processing Section
Literal
Address
RAM &
Operation
Data IO
Accumulator Registers
Instruction
Program Register
Internal data bus
Memory

Address
ALU
Instruction
STACK Program Counter Decoder IO
FLAG &
Special
Set up Function
Modify Set up
Registers
Clock
Reset Timing, Control and Register selection
Interrupts
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Source: Makis Malliris & Sabir Ghauri, UWE
Registers

CLK – Clock
CD – Clear/Reset
LD – Load

• Capable of storing a set of bits

• Built using Flip Flops

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4-bit Register

Source: http://virtual-labs.ac.in/labs/cse10/reg_cnt_design.html

• This is called a parallel-in, parallel-out register

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4-bit Register (Cont.)

Source: www.edwardbosworth.com 10
4-bit Serial-In, Serial-Out Register

Source: http://virtual-labs.ac.in/labs/cse10/reg_cnt_design.html

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Internal Structure

Address Bus
B
PC
+1 C
ALU
D

E
Data Bus

IR

Control Unit
ALU
FLAG
CTRL Bus

A
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Registers
• Type of memory located inside CPU
• Can hold a single piece of data
• Useful in both data processing & control functionalities
• Special purpose registers
• Program Counter (PC)
• Instruction Register (IR)
• Accumulator or working register
• Flag/Status register
• General purpose registers
• Used to store data

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Special Purpose Registers
Register Function
Accumulator (A) / Results of arithmetic & logic operations always go to
Working Register accumulator
(W) Connected directly to output of ALU
Program Counter Used to keep track of memory address of next instruction to
(PC) be executed
When instructions are fetched, instruction pointed by PC is
fetched into CPU
Once the instruction is fetched, PC is updated to point to
next instruction, i.e.,
PC = PC + d
Instruction Register Once fetched, instructions are stored in IR for execution
(IR) Located closely to control unit, which decodes the
instruction

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FLAG/STATUS Register
• Individual bits indicate status of ALU operations

Source: www.plantation-productions.com/Webster/www.artofasm.com/Linux/HTML/RealArithmetic.html
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Sample Program
100 Load A,10
100: Load A,10 101 Load B,15
101: Load B,15 102 ADD A,B
102: Add A,B 103 STORE A,[20]
103: STORE A,[20] 104

105
Program memory

18 00

19 00

20 00

21 00

Data memory 16
Instruction Execution Sequence
1. Fetch next instruction from memory to IR
2. Change PC to point to next instruction
3. Determine type of instruction just fetched
4. If instruction needs data from memory, determine
where it is
5. Fetch data if needed into register
6. Execute instruction
7. Go to step 1 & continue with next instruction

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Before execution of 1st fetch cycle
B

Address Bus
100
+1 C
ALU
D

IR E
Data Bus

Control Unit

ALU
CTRL Bus

FLAG
A

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Source: Dr. Chathura de Silva, CSE, UoM
After 1st fetch cycle …
B

Address Bus
101
+1 C
ALU
D

E
Data Bus
Load A,10

Control Unit

ALU
CTRL Bus

FLAG
A

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After 1st instruction cycle …
B
101

Address Bus
+1 C
ALU
D

Load A,10 E
Data Bus

Control Unit

ALU
CTRL Bus

FLAG
10

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Sample Program (Cont.)
100: Load A,10
101: Load B,15
102: Add A,B

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After 2nd fetch cycle …
B

Address Bus
102
+1 C
ALU
D

E
Data Bus
Load B,15

Control Unit

ALU
CTRL Bus

FLAG
A

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After 2nd instruction cycle …
B
15
102

Address Bus
+1 C
ALU
D

Load B,15 E
Data Bus

Control Unit

ALU
CTRL Bus

FLAG
10

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Sample Program (Cont.)
100: Load A,10
101: Load B,15
102: Add A,B

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After 3rd fetch cycle …
15

Address Bus
103
+1 C
ALU
D

E
Data Bus
ADD A,B

Control Unit

ALU
CTRL Bus

FLAG
10

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After 3rd instruction cycle …
15
103

Address Bus
+1 C
ALU
D

ADD A,B E
Data Bus

Control Unit

ALU
CTRL Bus

FLAG
25

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Programming Hierarchies

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Source: Introduction to PIC Microcontroller – Part 1 by Khan Wahid
Building Digital Solutions to
Computational Problems
· Labs & design project
· Product specs

· Algorithms, RTL, etc.

· Flowcharts
· State transition diagrams

· Logic equations
· Circuit schematics
· Verilog or VHDL code
· Assembler
· C, C++
· TTL Gates (AND, OR, XOR ... )
· Programmable Logic
· Custom ASICs
· FPGAs
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· MCs, DSPs
Thank you
Dr. Sulochana Sooriyaarachchi
sulochanas@cse.mrt.ac.lk
0776691011