Flash ADC (Parallel ADC) – Deep Dive

1. Concept Overview

A Flash ADC is the fastest type of analog-to-digital converter. It performs A/D conversion
in a single step by using a resistor ladder network and a bank of comparators, followed by
a priority encoder.

2. Architecture

✳️Main Components:

1. Resistor Ladder Network:

o Divides the reference voltage range [Vref−,Vref+][V_{\text{ref}^-}, V_{\
text{ref}^+}] into 2N−12^N - 1 equally spaced voltage levels for an N- bit
converter.
o Typically uses 2N2^N resistors.
2. Comparator Array:
o Each comparator compares the input voltage (VinV_{in}) with a different
reference voltage from the resistor ladder.
o Outputs ‘1’ if Vin>VrefV_{in} > V_{\text{ref}}, otherwise ‘0’.
3. Thermometer Code Output:
o The array of comparator outputs forms a “thermometer code”: a string of ones
followed by zeros.
4. Encoder (Thermometer-to-Binary Converter):
o Converts the thermometer code to binary format.

📊 Example: 3-bit Flash ADC

 Number of comparators = 23−1=7, Number of voltage levels = 8

 Encoder maps the 7-bit thermometer code to a 3-bit binary output.

⚙️3. Operation

1. The analog input Vin is compared simultaneously by all comparators.

2. The position in the resistor ladder where Vin crosses a reference level
determines how many comparators output ‘1’.
3. The encoder converts this position into a digital binary code.

🔬 4. Advantages

Feature Description
Speed Fastest conversion — one clock cycle.
 Feature Description
Simplicity Straightforward concept, suitable for low-bit systems.
Low Latency No pipeline delays or iterative steps.

⚠️5. Disadvantages

Issue Explanation
Exponential Number of comparators grows as 2N−12^N - 1 — impractical for >8-
Growth bit ADCs.
Power Hungry Each comparator consumes static and dynamic power.
Large Die Area Resistor ladder and comparator bank consume large silicon area.
Mismatch Offset voltages and gain errors in comparators introduce INL/DNL
Sensitivity errors.

• 6. Design Challenges in Mixed-Signal ICs

In mixed-signal systems (like RF receivers, data converters), Flash ADCs are often used in
subsystems (e.g., inside pipelined stages) rather than as full ADCs due to power and area
constraints.

A. Comparator Offset & Mismatch:

 Offset voltages lead to incorrect threshold detection.

 Requires calibration or offset trimming.
 Layout techniques (like common-centroid, interdigitated matching) are used to
minimize mismatch.

B. Reference Ladder Accuracy:

 Resistor ladder must be linear and matched.

 Process variations affect resistance ratios, introducing non-linearity.

C. Clock Feedthrough & Kickback:

 When the comparator switches, it can inject charge back to the input.
 Use buffer stages or sample-and-hold circuits to isolate sensitive analog front-
end.

D. Power Supply Noise:

 Since all comparators switch simultaneously, they generate large transients.

 Requires decoupling capacitors, power domain isolation, or clock skewing.

🔌 7. Use in Mixed-Signal Architectures

✅ Applications:

 As first-stage ADC in pipelined ADCs (e.g., 1.5-bit flash sub-ADCs).

 As part of time-interleaved ADCs (one of many parallel channels).
 As coarse quantizer in SAR-assisted ADCs.
 In digital oscilloscopes, GHz-range data acquisition, and radar.

🔄 Integration Techniques:

 Fully Differential Design: Improves immunity to common-mode noise.

 Digital Calibration: Corrects offset and gain errors digitally.
 Subranging & Folding Flash: Reduces comparator count via hybrid architectures.

◻ 8. Performance Metrics

Parameter Description
ENOB Effective number of bits — depends on comparator mismatch and jitter.
INL/DNL Integral/Differential Nonlinearity — affected by resistor and comparator
variation.
SNR/THD Signal-to-noise and harmonic distortion.
Power
Measured in fJ/conversion-step — important for mobile/IoT use.
Efficiency

📘 9. Real-World Examples
 4-bit Flash ADC at 2–4 GHz used in ultrafast sampling circuits.
 Flash ADC blocks embedded in successive stages of pipelined ADCs (1.5-bit/stage).
 ADCs for ultra-wideband communication (UWB) systems.

📌 10. Summary

Aspect Summary
Why use Flash? When speed is critical and bit resolution is modest.
Why not use When power, area, or resolution >8 bits is a concern.
Flash?
In Mixed-Signal Often used as sub-blocks, not full ADCs, with calibration and power
ICs? management.
◻ Two-Step Type ADC – Deep Dive

✅ 1. What is a Two-Step ADC?

A Two-Step ADC (also known as a Subranging ADC) divides the analog-to-digital

conversion process into two sequential steps:

1. Coarse Conversion: Finds the most significant bits (MSBs).

2. Fine Conversion: Measures the residue (the error between the actual input and the
DAC output of the coarse stage) to find the least significant bits (LSBs).

🔁 The result is the combination of coarse + fine results, giving a high-resolution output
with reduced hardware complexity compared to a full-resolution flash ADC.

◻ 2. Architecture & Block Diagram

Vin
|
[ Sample & Hold ]
|
[ Coarse ADC (e.g., Flash) ] --> [DAC]
| |
Coarse Code |
| |
> [Subtractor] <

|
|
Residue
(Error)
|
[ Fine ADC
(e.g., SAR)]
|
Fine Code
|
[ Digita
l Combiner ]
⚙️3. Detailed Operation |
Final
Digital
Assume an N-bit ADC split into:
Output
 Coarse ADC = M bits
 Fine ADC = (N - M) bits

Steps:

1. Sample & Hold:

 o Captures the analog input signal (VinV_{\text{in}}) to maintain stability
during conversion.
2. Coarse Conversion:
o A fast, low-resolution ADC (often a flash) estimates the MSBs of
Vin
o Outputs coarse digital code (DM).
3. Digital-to-Analog Conversion (DAC):
o Converts the coarse digital output back into an analog signal
DAC
4. Residue Generation:
o Residue = Vin−VDAC
o This analog error is amplified and sent to the fine ADC.
5. Fine Conversion:
o A slower but higher-resolution ADC (e.g., SAR) resolves
the residue.
o Outputs LSBs (D(N−M).
6. Digital Combination:
o Final output = concatenate DM and DN−M

📊 4. Key Example

Let’s say you want an 8-bit ADC:

 Use 4-bit Coarse ADC (Flash): outputs 4 MSBs

 Use 4-bit Fine ADC (SAR or Flash): resolves 4 LSBs
 Hardware cost is much lower than an 8-bit Flash ADC (255 comparators vs. 2×15 +
DAC)

◻ 5. Advantages

Feature Description
Reduced Comparator Count Far fewer comparators than a pure flash ADC.
Faster than SAR ADC Faster total conversion due to partial flash-based coarse step.
High Resolution Possible Easily scale to 10–12 bits without exploding hardware cost.
Efficient for Medium Speeds Used in moderate-speed ADCs (10–200 MSps).

⚠️6. Design Challenges in Mixed-Signal ICs

In a mixed-signal environment, implementing a Two-Step ADC has several analog and

digital integration challenges:

A. Mismatch and Nonlinearity

  DAC errors or mismatches in residue generation can lead to missing codes or
nonlinearity.
 Trim/calibration needed for gain, offset, and DAC linearity.

B. Precision Subtraction

 Residue generation requires high-precision analog subtraction, often with gain.

 Analog subtractor must be linear, fast, and low-noise.

C. Clock Synchronization

 Timing between the coarse and fine steps must be precise.

 Involves complex sample-and-hold timing and digital synchronization logic.

D. Noise Sensitivity

 Analog operations (subtraction, DAC) must be shielded from digital switching noise.
 Requires layout isolation, guard rings, and low-impedance ground planes.

E. Speed vs Accuracy Tradeoff

 Coarse step is fast, but fine step (e.g., SAR) may limit speed.
 Critical to balance stage resolution (e.g., 5+5 or 6+4 bits in a 10-bit ADC).

🔧 7. Enhancements in Modern Two-Step ADCs

 Redundant Bits: Allow for digital correction of coarse/fine boundary errors.
 Calibration Techniques: Background digital calibration corrects DAC or comparator
errors.
 Digital Gain Correction: Gain mismatches in fine stage corrected digitally.
 Shared DACs: Resource sharing between coarse/fine stages for area saving.

8. Typical Use in Mixed-Signal SoCs

 Audio Codecs: 10–12 bits, 100s of kSps to few MSps.
 Wireless RF Front-Ends: Moderate resolution (10–12 bits), 10–100 MSps.
 Imaging Sensors: Column-parallel Two-Step ADCs with shared analog front ends.

◻ 9. Performance Metrics

Metric Notes
Resolution Typically 10–12 bits
 Metric Notes
Speed 1–200 MSps
ENOB ~8–10 bits after correction
Power Efficiency More efficient than full flash, better than pure SAR
Area Moderate (lower than full flash ADCs)

🔚 10. Summary

Feature Flash ADC Two-Step ADC

Speed Ultra-fast Moderate-fast
Power High Lower
Resolution Limited (<8 bits) Moderate to high (10–12 bits)
Complexity Exponential growth Scalable
Application High-speed sampling Mixed-signal SoCs, imaging, RFICs

Algorithmic (Cyclic) ADC – Deep Dive

✅ 1. What is an Algorithmic ADC?

An Algorithmic ADC performs A/D conversion by recycling the same hardware over
multiple cycles to extract bits one-by-one (or in small groups). It’s also called a Cyclic ADC
because the conversion process is iterative, cycling through the same analog circuit block.

🔁 Unlike SAR ADCs (which use binary search), algorithmic ADCs use residue
amplification and subtraction repeatedly.

◻ 2. Core Architecture & Block Diagram

Main Components:

1. Sample and Hold (S/H)

2. 1-bit Flash ADC
3. 1-bit DAC
4. Amplifier (Gain = 2)
5. Control Logic

📊 Block Diagram (1-bit per cycle example)

Vin
|
 [ Sample & Hold ]
|
Residue Register
| |
[ Comparator (1-bit ADC) ] |
| |
[ 1-bit DAC ] |
| |
[ Subtractor ] |
|

|
[ Amplifier (Gain = 2) ] -------------
|
Residue → Next Cycle (Stored)

Each clock cycle:

 One bit is resolved.

 Residue is updated and used for the next iteration.

For an N-bit resolution, it takes N clock cycles.

⚙️3. How It Works (1-bit Example)

At each cycle i:

1. Compare the input or current residue with mid-range (Vref/2):

o If Vin>Vref/2V_{\text{in}} > V_{\text{ref}}/2, output bit is 1
o Else, output bit is 0
2. Generate analog equivalent (1-bit DAC) of this decision.
3. Subtract the DAC output from the input/residue.
4. Amplify the result by 2 (gain = 2) to prepare for the next cycle.
5. Repeat for N cycles → Get all N bits.

◻ Example: 3-bit Conversion

 Cycle 1: MSB determined

 Cycle 2: Next bit from amplified residue
 Cycle 3: LSB determined

Final output is concatenated: [MSB][bit1][LSB]

📐 4. Mathematical Insight

Each cycle computes:

Vi+1=2×(Vi−Di⋅Vref/2)V_{i+1} = 2 \times (V_i - D_i \cdot V_{\text{ref}}/2)

Where:

 ViV_i: Residue input at cycle i

 DiD_i: Digital bit output at cycle i

📈 5. Advantages

Feature Description
Area-Efficient Same hardware reused over cycles (very compact).
Low Power Ideal for low-power SoCs (e.g., sensors, wearables).
Medium Resolution Good for 8–12 bit resolution.
Digital-Like Design Simplifies layout and control logic in digital-dominant
environments.
Well-Suited for
Ideal for mixed-signal designs where area and power are tight.
Integration

⚠️6. Disadvantages

Limitation Cause
Limited Speed Requires N cycles for N bits (vs. flash = 1 cycle).
Analog Block Accuracy Subtractor, DAC, and amplifier must be highly linear and
matched.
Noise Accumulation Analog noise and residue errors can accumulate with each cycle.
Gain Error Sensitivity Small amplifier gain deviations compound over cycles.

7. Use in Mixed-Signal Design

Why Algorithmic ADC is popular in Mixed-Signal SoCs:

 Compact: Uses minimal analog hardware → saves silicon area.

 Easy Clocking: Single clock domain, no complex timing.
 Good Digital Control: Works well with FSM or microcontroller.
 Low-speed but high-accuracy needs → e.g., sensor readouts, power monitors.

Typical Applications:

 CMOS Image Sensors (per-column ADCs)

 IoT Sensor Nodes (8–12 bits, low power)
 Battery Monitoring
 Capacitance/Resistance Sensing
Q 8. Design Challenges in Mixed-Signal Environments

A. Analog Block Accuracy

 Gain=2 amplifier must be precise and linear.

 Offset, gain, and common-mode rejection affect ADC linearity (INL/DNL).

B. Switching Noise Isolation

 Digital blocks (control, counters) must not inject noise into analog core.
 Use deep n-wells, guard rings, and isolation techniques.

C. Clock Jitter

 Though tolerant to jitter per cycle, phase noise can shift comparator behavior.
 Clock buffers should be shielded.

D. Temperature Drift

 Analog errors (amplifier offset, reference variation) worsen with temperature.

 Often need background calibration or auto-zeroing.

E. DAC Mismatch

 Mismatched 1-bit DAC reference levels can bias all conversion steps.

Techniques to Improve Performance

 Digital Calibration: Estimate and correct gain/offset digitally.
 Redundant Algorithmic ADC: Add redundancy to tolerate errors.
 Pipelined-Cyclic ADC: Combine cyclic architecture with pipelining for higher speed.
 Fully Differential Design: Improves linearity and noise immunity.
 Auto-Zero Techniques: Compensate amplifier offset in each cycle.

Performance Summary

Parameter Typical Range

Resolution 8–12 bits
Speed ~10 kSps to 10 MSps
Power Low (<1 mW typical)
Area Very Small
ENOB ~9–11 bits (with calibration)
 Example Use Case

In a CMOS image sensor, a 10-bit cyclic ADC is placed at each column:

 Minimal area per column.

 Converts pixel output row-by-row.
 Low power and compact control logic.

Summary

Feature Description
Key Benefit Compact and power-efficient due to hardware reuse
Limitation Speed limited by N-cycle operation
Best Fit Low-speed, medium-resolution ADC in mixed-signal SoCs
Common Applications Sensors, imagers, biomedical chips, battery monitors

Interpolation ADC – Deep Dive

Interpolation ADC

An Interpolation ADC enhances the resolution and reduces hardware complexity (especially
comparator count) in flash-type ADCs by interpolating between comparator levels instead
of using a unique comparator for every voltage step.

This technique enables:

 Fewer front-end comparators

 Higher resolution
 Lower power and area
 Still achieving very high speed

Why we Use Interpolation

In a conventional N-bit flash ADC, you need 2^N - 1 comparators.

For example: 8-bit resolution → 255 comparators!

To reduce this:

 Use Interpolation to digitally or analogically estimate the "in-between" values.

Interpolation =

 Reconstructing missing intermediate comparator thresholds using fewer reference

points.

3. Interpolation ADC Architecture

A. Typical Structure

1. Preamp Stages
o Front-end amplifiers handle input signal and drive interpolation.
2. Interpolator Network
o Generates intermediate levels between preamplifier outputs.
3. Latched Comparators
o Sample the interpolated signals to produce digital output.
4. Encoder & Bubble Correction
o Converts raw thermometer code to binary and fixes errors.

4. Types of Interpolation

Type Description
Resistive Interpolation Uses resistor ladders between amplifiers or comparators.
Capacitive Interpolation Replaces resistors with capacitors – lower power.
Active Interpolation Uses amplifier-based interpolators for better speed and matching.

5. Example – 6-bit Flash with Interpolation

Instead of 63 comparators:

 Use 15 preamp outputs

 Interpolate 4 intermediate values per stage
 Get 60 interpolated levels
 Total effective resolution: 6 bits

Benefits:

 ~75% reduction in comparator count

 Less power and area
6. Interpolation ADC in Mixed-Signal ICs

Why it’s used:

Advantage Benefit in Mixed-Signal SoCs

Lower Area Saves silicon on high-res flash ADCs
Power Efficiency Fewer comparators = less dynamic/static power
High-Speed Still supports GHz sampling rates
Integration-Friendly Matches well with RF/digital blocks

Typical Applications:

 High-speed wireline interfaces (e.g., SerDes, CDRs)

 RF receivers (Wi-Fi, LTE, 5G)
 High-speed oscilloscopes
 High-performance data converters in DSP chains

7. Design Challenges in Mixed-Signal Integration

A. Linearity (INL/DNL) differential and integral nonlinearity –

 Interpolated outputs must be linear and monotonic.

 Resistor and capacitor mismatch can cause distortion.

B. Noise Coupling

 Fewer comparators → preamps handle more analog bandwidth.

 Susceptible to substrate noise from digital switching.

C. Offset and Gain Mismatch

 Front-end amplifiers must be well-matched.

 Calibrations or trimming often needed.

D. Power-Delay Tradeoff

 Active interpolation adds gain and speed, but also consumes more power.

8. Techniques to Improve Interpolation ADCs

 Technique Purpose
Offset Calibration Removes comparator mismatch for better accuracy
Digital Background Adapts over temperature/voltage shifts
Calibration
Differential Architectures Reduces common-mode noise and distortion
Low-jitter clock design Critical for high-speed input tracking
Lower power than resistive, but harder to control
Capacitive Interpolation
matching

9. Performance Metrics

Metric Typical Range

Resolution 6–8 bits
Speed 100 MSps – 2 GSps+
Power Moderate (depends on interpolation type)
Area Smaller than equivalent flash ADC
INL/DNL ≤ 1 LSB (after calibration)

10. Summary

Feature Description
Key Benefit Reduces comparator count in high-speed ADCs
Resolution Typically 6–8 bits
Speed Very high (GHz range)
Application Mixed-signal SoCs, RF receivers, SerDes, DSP
Challenge Requires precise matching, linearity, and calibration

Folding ADC – Deep Dive

Folding ADC

A Folding ADC reduces the number of comparators required in a high-speed, medium-

resolution flash ADC by "folding" the analog input range into multiple sub-ranges. These
folded versions are then processed using a small number of comparators to resolve fine
digital outputs.

Instead of covering the entire voltage range with unique comparator levels (as in full
flash), a Folding ADC reuses the same comparator range multiple times, increasing
efficiency without sacrificing speed.
🔁 2. Why “Folding”?

Think of folding like bending the input signal waveform so that different parts of the voltage
range map to overlapping regions, which can be resolved using fewer comparators.

For example:

 Instead of 64 comparators for a 6-bit flash ADC,

 Use 8 coarse comparators and 4x folding → only need ~24 comparators.

◻ 3. Architecture of Folding ADC

◻ Main Components:

1. Track-and-Hold Circuit
2. Folding Circuit (Analog Preprocessing)
3. Coarse ADC (Flash or Interpolated)
4. Fine ADC (Low-resolution Flash)
5. Encoder (Digital logic to merge coarse and fine outputs)

📊 4. How Folding Works – Conceptually

Let’s say the input range is divided into folds using a folding factor MM. This results in:

 Coarse ADC: Identifies which fold the input falls into.

 Folding Circuit: Folds the input into a base interval (like normalizing it).
 Fine ADC: Determines position within that fold.

Example: 6-bit Folding ADC with 4× Folding

 64 levels total (6 bits)

 Use 16 comparators for folding circuit (coarse)
 4 comparators for fine (interpolation)
 Final result = combine coarse + fine

◻ 5. Mathematical Model

Let:

 NN: Total bits (e.g., 6)

 MM: Folding factor
  K=2NK = 2^N: Total levels

Then:

 Coarse resolution: log⁡2(K/M)\log_2(K / M)

 Fine resolution: log⁡2(M)\log_2(M)

Final ADC output = (Coarse index)×M+Fine index(\text{Coarse index}) \times M +

\text{Fine index}

⚙️6. Folding Circuit Operation

The folding circuit creates a nonlinear analog function that "folds" the input:

 It is often a multi-slope waveform resembling a triangle or sawtooth.

 Implemented using differential pair arrangements or piecewise-linear shaping.

The same output voltage range is reused to represent multiple segments of the input range
→ significantly reduces the number of comparators needed.

⚡ 7. Advantages of Folding
ADCs
Feature Description
High Speed Suitable for GHz sampling rates
Reduced Comparator Major savings vs full flash (especially at ≥6 bits)
Count
Lower Power Fewer comparators means reduced static and dynamic power
Lower Area Especially valuable in mixed-signal ICs with tight area
constraints
Resolution can be increased with only marginal hardware
Scalable
overhead

⚠️8. Disadvantages

Limitation Cause
Linearity Issues Folding waveform must be precisely shaped to avoid INL/DNL
errors
Complex Gain/offset variations in folding circuit must be corrected
Calibration
Timing Mismatch Coarse and fine paths must be tightly synchronized
Design Complexity More challenging than flash or SAR due to analog pre-processing
◻ 9. Use in Mixed-Signal ICs

Why Folding ADCs are favored in mixed-signal design:

 Combine high speed and low comparator count

 Well-suited for digitally assisted analog calibration
 Integrates efficiently in RF, communication, and DSP SoCs

Typical Applications:

 High-speed wireless receivers (e.g., LTE, 5G)

 SerDes and data converters for multi-GSps transceivers
 Oscilloscopes and instrumentation
 Imaging ADCs in high-resolution sensors

◻ 10. Design Considerations in Mixed-Signal ICs

Challenge Design Solution

Analog Folding Accuracy Use auto-zeroed or digitally calibrated folding circuits
Mismatch & Nonlinearity Use interpolation + calibration
Clocking Issues Careful clock tree synthesis and layout symmetry
Substrate Noise Deep n-well, differential design, guard rings

11. Enhancements

Technique Purpose
Digital Calibration Correct offset, gain, and non-linearity errors
Interpolation + Folding Hybrid ADCs use folding for coarse, interpolation for fine steps
Redundancy Improves yield and reduces error sensitivity
Fully Differential Design Noise and distortion immunity

📈 12. Performance Summary

Parameter Range
Resolution 6–10 bits
Speed > 500 MSps to several GSps
Comparator Count ~20–30% of full flash
Power Lower than full flash
Linearity (with calibration) INL/DNL < 1 LSB
🔚 13. Summary

Feature Description
Key Benefit High-speed ADC with reduced comparator count
Main Use Communication systems, RF receivers, DSP front ends
Typical Resolution 6–10 bits
Core Technique Folds input range to reuse comparators