8086

Microprocess
or
Case Study: Intel
Slide 2
Processors
 Micropro
Fifth Generation Pentium

ce Fourth Generation
During 1980s
Low power version of HMOS technology

ssor Third Generation

During 1978 HMOS technology  Faster
(HCMOS)
32 bit processors
Physical memory space 224 bytes = 16 Mb
speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density 16 bit processors  40/ 48/ Floating point hardware
64 pins Supports increased number of addressing
Easier to program Dynamically modes
relatable programs Processor has multiply/
divide arithmetic Intel 80386
hardware More powerful interrupt handling
capabilities
Flexible I/O port addressing Second Generation
During 1973
Intel 8086 (16 bit processor) NMOS technology  Faster speed, Higher
density, Compatible with TTL
First Generation 4 / 8/ 16 bit processors  40 pins Ability
Between 1971 – 1973 PMOS technology, to address large memory spaces and I/O
non compatible with TTL ports
4 bit processors  16 pins Greater number of levels of subroutine
8 and 16 bit processors  40 pins Due to nesting
limitations of pins, signals are Better interrupt handling capabilities
multiplexed 3
Intel 8085 (8 bit processor)
8086
Microprocessor Overview

First 16- bit processor released Addressabl memory space

by e
is organized in to two banks of 512 kb
INTEL in the year 1978 each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to

𝐁𝐇𝐄 is used to access odd bank

Originally HMOS, now manufacture select even bank and control signal
using HMOS III technique d

Uses a separate 16 bit

Approximately 29, 000 transistors, 40 address for I/O mapped devices  can
pin DIP, 5V supply generate 216 = 64 k addresses.

Operates in two modes:

decided by the signal at MN and 𝐌𝐗

Does not have internal clock; external minimum mode and maximum mode,
asymmetric clock source with 33%
duty cycle pins.

20-bit address to access memory  can

address up to 220 = 1 megabytes
of memory space.

4
8086
Microprocessor Pins and Common signals
Signals
AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus.

These are multiplexed with status
signals
5
8086
Microprocessor Pins and Common signals
Signals
BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It is
multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal. It is active when low.

6
8086
Microprocessor Pins and Common signals
Signals
TEST

𝐓𝐄𝐒𝐓 input is tested by

the ‘WAIT’
instruction.

8086 will enter a wait state after

execution of the WAIT instruction and

𝐓𝐄𝐒𝐓 is made low by an active

will resume execution only when the

hardware.

This is used to synchronize an external

activity to the processor internal
operation.
READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active 7

8086
Microprocessor Pins and Common signals
Signals
RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized 8
8086
Microprocessor Pins and Min/ Max Pins
Signals

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocesso systems.
r

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

9
8086
Microprocessor Pins and Minimum mode signals
Signals
Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is

tied
to VCC (logic high)

8086 itself generates all the bus control signals

DT/𝐑ഥ
(Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers

𝐃𝐄
𝐍
(Data Enable) Output signal from the processor
used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

𝐈𝐎
M/ Used to differentiate memory access and I/O
access. For memory reference instructions, it
is

𝐖
high. For IN and OUT instructions, it is low.

𝐑
Write control signal; asserted low Whenever
processor writes data to memory or I/O port

𝐈𝐍𝐓
𝐀
(Interrupt Acknowledge) When the interrupt
request is accepted by the processor, the output
is
low on this line.
10
8086
Microprocessor Pins and Minimum mode signals
Signals
Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the
control of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

11
8086
Microprocessor Pins and Maximum mode signals
Signals
During maximum mode operation, the MN/ 𝐌𝐗
is grounded (logic low)

Pins 24 -31 are reassigned

𝑺𝟎,
𝑺𝟏 , 𝑺𝟐
Status signals; used by the 8086 bus controller to
generate bus timing and control signals. These
are decoded as shown.

12
8086
Microprocessor Pins and Maximum mode signals
Signals
During maximum mode operation, the MN/ 𝐌𝐗
is grounded (logic low)

Pins 24 -31 are reassigned

𝑸𝑺𝟎,
𝑸𝑺𝟏
(Queue Status) The processor provides the status
of queue in these lines.

The queue status can be used by external device

to
track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

13
8086
Microprocessor Pins and Maximum mode signals
Signals
During maximum mode operation, the MN/ 𝐌𝐗
is grounded (logic low)

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎,
𝐑𝐐/𝐆𝐓𝟏
(Bus Request/ Bus Grant) These requests are used
by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on𝐆𝐓𝟎 will have higher priority

than𝐆𝐓𝟏

𝐋𝐎𝐂
𝐊
An output signal activated by the LOCK prefix
instruction.

Remains active until the

completion of the
instruction prefixed by LOCK.

The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.

14
 8086
Architectur
e Microprocessor

15
8086
Microprocessor Architectur
e

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that BIU fetches instructions, reads data

have already been fetched by the from memory and I/O ports, writes
BIU. data to memory and I/ O ports.
BIU and EU functions separately.
16
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e
Dedicated Adder to
generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS) Data

Segment (DS) Stack
Segment (SS) Extra
Segment (ES)

Segment Registers >> 17

8086
Microprocessor Architectur
e
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

18
8086
Microprocessor Architectur Registers and Special
e Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE and
LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 19
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e

Segment
Registers

8086’s 1-megabyte The 8086 can Programs obtain access

memory is divided directly address four to code and data in the
into segments of up (256 Ksegments
bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

20
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e

Segment Code Segment

Registers Register
16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then
offset is added provided by the IP.

21
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e

Segment Data Segment

Registers Register
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.

22
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e

Segment Stack Segment

Registers Register
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and
the Base Pointer (BP).

23
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e

Segment Extra Segment

Registers Register
16-bit

Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the

20-
bit physical address for the destination.

24
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed

within
the currently executing code segment.

So, this register contains the 16-bit offset address

pointing to the next instruction code within the 64Kb of
the code segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.

25
8086
Architectur Bus Interface Unit (BIU)
Microprocessor
e

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.

This is done in order to

speed up the execution
by overlappin
instruction g fetch with
execution.

This mechanism is known

as pipelining.

26
8086
Architectur Execution Unit (EU)
Microprocessor
e
EU decodes and
executes instructions.

A decoder in the EU
control system
translates
instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can
Index registers (Source be used as two 8 bit registers as
Index, Destination Index) :
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 27
DX can be used as DH and
8086
Architectur Execution Unit (EU)
Microprocessor
e

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX

or AL for inputting /
outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

28
8086
Architectur Execution Unit (EU)
Microprocessor
e

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

29
8086
Architectur Execution Unit (EU)
Microprocessor
e

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte

of
the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

30
8086
Architectur Execution Unit (EU)
Microprocessor
e

EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte

of
the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

32 ÷ 16 division and the 16-bit reminder after division.

multiplication or the high 16-bit dividend (data) before a

31
8086
Architectur Execution Unit (EU)
Microprocessor
e

EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment
in the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

32
8086
Architectur Execution Unit (EU)
Microprocessor
e

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

33
8086
Architectur Execution Unit (EU)
Microprocessor
e

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

34
 8086
Architectur Execution Unit (EU)
Microprocessor
eAuxiliary Carry Flag
Carry Flag
Flag This is set, if there is a carry
This flag is set, when
from the lowest nibble, i.e, bit
Register three during addition, or there is a carry out of
borrow for the lowest nibble, MSB in case of
i.e, bit three, during addition or a borrow
subtraction. in case of subtraction.
Sign Flag Zero Parity Flag
Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation is the computation or comparison byte of the result contains even
negative performed by an instruction is number of 1’s ; for odd number of
zero 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the
This flag is set, if an overflow occurs, i.e, if the result of a signed processor enters the
operation is large enough to accommodate in a destination
single step execution
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit mode by generating
sign operations, then the overflow will be set. internal interrupts
after the execution of
Direction Interrupt Flag
each instruction
Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 35
 ADDRESSING
MODES
& Instruction set
8086
Microprocessor Introduction

Program
A set of instructions written to solve
a problem.

Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.

Computer language

High Level Low Level

Machine Assembly Language

Language
⯀ Binary bits ⯀ English
Alphabets
⯀ ‘Mnemonics’
⯀ Mnemonics
Assembler Machine
37
Language
ADDRESSING
MODES
8086
Microprocessor Addressing
Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register
Addressing
Group I : Addressing modes for
2. Immediate register and immediate data
Addressing
3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing
memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing m4o0de

8086 Group I : Addressing modes for
Microprocessor Addressing register and immediate
Modes data

1. Register The instruction will specify the name of the

Addressing register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Example:
Addressing
4. Register Indirect Addressing
MOV CL,
5. Based DH
Addressing The content of 8-bit register DH is moved
6. Indexed Addressing to another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

41
8086 Group I : Addressing modes for
Microprocessor Addressing register and immediate
Modes data

1. Register
Addressing In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct
Example:
Addressing
4. Register Indirect Addressing
MOV DL,
5. Based 08H
Addressing The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String
Addressing MOV AX,
9. Direct I/O port Addressing 0A9FH
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

42
8086
Microprocessor Addressing Modes : Memory
Access
20 Address lines  8086 can address up to
2 = 1M bytes of memory
20

However, the largest register is only 16 bits

Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto
the address bus.

Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 16 10), then add the contiguous memory
required offset to form the 20- bit address

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte
unit)
+ -------
98AC2 (The absolute address) 44
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct
Addressing location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based The effective address is just a 16-bit number

Addressing written directly in the instruction.
6. Indexed Addressing
Example:
7.
MOV BX, [1354H]
8. String Based BL, [0400H]
MOV
Addressing Index
9. Direct I/O port Addressing Addressin
The
g square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents
11. Relative Addressing of the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

46
 Group II : Addressing modes
8086
Addressing Modes
for memory data
Microprocessor

1. Register In Register indirect addressing, name of the

Addressing register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Registers used to hold EA are any of the following

Addressing registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of register is used for
6. Indexed Addressing
the DS base
7. Based Index Addressing address calculation.
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer to
MOV CX, [BX]
content of register/
9. Direct I/O port Addressing memory
Operations
10. Indirect I/O port Addressing :
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA)
or,

(CL)  (MA)
(CH)  (MA +1) 47
 8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register In Based Addressing, BX or BP is used to hold the
Addressing base value for effective address and a signed 8-
2. Immediate Addressing or unsigned 16-bit displacement will be specified
bit
in the instruction.
3. Direct
Addressing In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base

value of EA, 20-bit
6. Indexed Addressing
physical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations
11. Relative Addressing :
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
48
(AH)  (MA + 1)
 8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register SI or DI register is used to hold an index value for
Addressing memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct
Addressing Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based In case of 8-bit displacement, it is sign extended

Addressing to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String
Addressing MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations
10. Indirect I/O port Addressing :
FFA2H  A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H BA = (DS) x
12. Implied Addressing 1610 MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
49
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register In Based Index Addressing, the effective address
Addressing is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct
Addressing Example:
4.Register Indirect
Addressing
MOV DX, [BX + SI + 0AH]
5.Based Addressing
Operations
6. Indexed Addressing
:
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String EA = (BX) + (SI) + 000AH BA =

Addressing (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX)  (MA) or,

11. Relative Addressing (DL)  (MA)

(DH)  (MA + 1)
12. Implied Addressing

50
8086 Group II : Addressing modes
Microprocessor Addressing for memory data
Modes
1. Register Employed in string operations to operate on
Addressing string data.
2. Immediate Addressing
The effective address (EA) of source data is
3. Direct stored in SI register and the EA of destination is
Addressing stored in DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based source data is DS and that of the destination data
Addressing is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS
8. String Addressing BYTE
Operations
9. Direct I/O port Addressing :
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE +
12. Implied Addressing
EAE

Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1 If
DF = 0, then (SI)  (SI) +1 and (DI) = (DI)51+ 1
8086 Group III : Addressing
Microprocessor Addressing modes for I/O ports
Modes
1. Register These addressing modes are used to access data
Addressing from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit
3. Direct port
Addressing address is directly specified in the instruction.
4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Operations PORTaddr = 09H

Addressing : (AL)  (PORT)
6. Indexed Addressing
Content of port with address 09H is
7. Based Index Addressing
moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.

11. Relative Addressing Example: OUT [DX], AX

12. Implied Addressing Operations: PORTaddr = (DX)

(PORT)  (AX)

Content of AX is moved to port

whose address is specifiedby DX
register. 52
8086 Group IV : Relative
Microprocessor Addressing Addressing
Modes mode

1. Register Addressing

2. Immediate Addressing

3. Direct In this addressing mode, the effective address of

Addressing a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based
Addressing Example: JZ 0AH
6. Indexed Addressing
Operations
7. Based Index Addressing
:
8. String 000AH  0AH (sign extend)
Addressing
9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA
12. Implied Addressing If ZF = 1, then the program control jumps to
new address calculated above.

If ZF = 0, then
next instruction of
the program is executed. 53
 8086 Group IV : Implied
Microprocessor Addressing Addressing
Modes mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String
Addressing Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to
10. Indirect I/O port Addressing zero.

11. Relative
Addressing

12. Implied Addressing

54
INSTRUCTION
SET
8086
Microprocessor Instruction Set

8086 supports 6 types of instructions.

1.Data Transfer Instructions

2.Arithmetic Instructions

3.Logical Instructions

4.String manipulation Instructions

5.Process Control Instructions

6.Control Transfer Instructions

56
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate

data Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

57
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN,

OUT …
MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 MOV mem, reg1(reg2)  (reg1)

MOV reg2, mem (mem)  (reg1)
(reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

58
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN,

OUT …
PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP (MA S ; MA S + 1) 
(reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP (MA S ; MA S + 1) 
(mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
59
8086
Microprocessor Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN,

OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX) (PORT)

(AL)  (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX) (PORT)

(AX)  (PORT)  (AX)

IN A, addr8 IN OUT addr8, A OUT

AL, addr8 IN (AL)  (addr8) addr8, AL OUT (addr8)  (AL)

AX, addr8 (AX)  (addr8) addr8, AX (addr8)  (AX)

60
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem

ADC reg2, reg1 ADC reg2, mem ADC(reg2)  (reg1) + (reg2) (reg2)  (reg2) +
mem, reg1 (mem)
(mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

61
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
ADC reg2/ mem, reg1/mem

ADC reg2, reg1 ADC reg2, mem ADC(reg2)  (reg1) + (reg2)+CF (reg2)  (reg2)
mem, reg1 + (mem)+CF (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF

62
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
SUB reg2/ mem, reg1/mem

SUB reg2, reg1 SUB reg2, mem SUB(reg2)  (reg1) - (reg2)

mem, reg1 (reg2)  (reg2) - (mem)
(mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

63
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
SBB reg2/ mem, reg1/mem

SBB reg2, reg1 SBB reg2, mem SBB(reg2)  (reg1) - (reg2) - CF

mem, reg1 (reg2)  (reg2) - (mem)- CF
(mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

64
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
INC reg/ mem

INC reg8 INC reg16 INC mem (reg8)  (reg8) + 1 (reg16)  (reg16) + 1

(mem)  (mem) + 1

DEC reg/ mem

DEC reg8 DEC reg16 DEC mem (reg8)  (reg8) - 1 (reg16)  (reg16) - 1

(mem)  (mem) - 1

65
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

66
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient (AH)  (AX) MOD(reg8)
Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

67
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient (AH)  (AX) MOD(reg8)
Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

68
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0 If

(reg2) < (reg1) then CF=1, ZF=0, SF=1 If (reg2)
= (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0 If

(reg2) < (mem) then CF=1, ZF=0, SF=1 If (reg2)
= (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0 If

(mem) < (reg1) then CF=1, ZF=0, SF=1 If (mem)
= (reg1) then CF=0, ZF=1, SF=0

69
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0 If (reg) <

data then CF=1, ZF=0, SF=1 If (reg) = data then
CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0 If (mem)

< data then CF=1, ZF=0, SF=1 If (mem) = data
then CF=0, ZF=1, SF=0

70
8086
Microprocessor Instruction Set

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, INC, DEC,
Mnemonics:
MUL, DIV, CMP…
CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0 If (AL) <

data8 then CF=1, ZF=0, SF=1 If (AL) = data8
then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

71
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

72
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

73
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

74
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

75
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

76
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

77
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

78
8086
Microprocessor Instruction Set

3. Logical Instructions
AND, OR, XOR, TEST, SHR,
Mnemonics:
SHL, RCR, RCL …

79
8086
Microprocessor Instruction Set

4. String Manipulation
Instructions
 String Sequence of bytes or words
:
 8086 instruction set includes instruction string movement, comparison,
scan,
for load and store.

 REP instruction : used to repeat execution of string

prefix instructions
 String instructions end with S or SB or SW.
S represents string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register

and
that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

80
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and (CX)  (CX) - 1
(Repeat CMPS or SCAS until
ZF = 1)

81
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2 If DF

= 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
82
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0 If

(MA) < (MAE), then CF = 1; ZF = 0; SF = 1 If (MA)
CMPSW = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1 If DF
= 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2 If DF
= 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
83
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0 If (AL) <

(MAE), then CF = 1; ZF = 0; SF = 1 If (AL) = (MA E), then
CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0 If

(AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1 If
(AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
84
If DF = 0, then (DI)  (DI) + 2 If DF = 1, then (DI)  (DI)
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI) (AL)  (MA)

If DF = 0, then (SI)  (SI) + 1 If DF = 1, then (SI)  (SI) –

1

MA = (DS) x 1610 + (SI)

LODSW (AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

85
8086
Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI) (MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1 If DF = 1, then (DI)  (DI)

–1

MAE = (ES) x 1610 + (DI)

STOSW (MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

86
8086
Microprocessor Instruction Set

5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus with
the 8086

LOCK Lock bus during next instruction 87

8086
Microprocessor Instruction Set

6. Control Transfer Instructions

Transfer the control to a specific destination or

target instruction Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

88
8086
Microprocessor Instruction Set

6. Control Transfer Instructions

 8086 signed  8086 unsigned
conditional branch conditional
instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the
same segment by modifying the content of IP

89
8086
Microprocessor Instruction Set

6. Control Transfer Instructions

 8086 signed  8086 unsigned
conditional branch conditional
instructions branch instructions
Name Alternate name Name Alternate name
JE disp8 Jump if JZ disp8 JE disp8 Jump if JZ disp8
equal Jump if result is 0 equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 Jump if JNBE disp8
Jump if greater Jump if not less or above Jump if not below
equal or equal
JGE disp8 Jump if JNL disp8 JAE disp8 JNB disp8
greater than or Jump if not less Jump if above or Jump if not below
equal equal
JL disp8 JNGE disp8 Jump if JB disp8 Jump if JNAE disp8
Jump if less than not greater than or below Jump if not above
equal or equal

JLE disp8 JNG disp8 Jump if JBE disp8 JNA disp8

Jump if less than or not greater Jump if below or Jump if not above
equal equal 90
8086
Microprocessor Instruction Set

6. Control Transfer Instructions

8086 conditional branch instructions

affecting individual flags
Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

91