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ORCIDDSD 2013: Los Alamitos, CA, USA
- 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-2978-8
DSD-1: Interconnect Design
- Guangda Zhang, Wei Song
, Jim D. Garside, Javier Navaridas, Zhiying Wang:
Transient Fault Tolerant QDI Interconnects Using Redundant Check Code. 3-10 - Shuo Li, Ahmed Hemani:
Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework. 11-17
DSD-2: SoC & NoC 1
- Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC. 21-28 - Pierre Bomel, Marc Sevaux:
Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations. 29-36
MSDA 1: Multicore Systems: Design and Applications
- Pavel G. Zaykov, Georgi Kuzmanov, Anca Mariana Molnos, Kees Goossens:
Run-Time Slack Distribution for Real-Time Data-Flow Applications on Embedded MPSoC. 39-47 - Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio:
Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs. 48-55
Poster Session 1
- Sandro Bartolini, Luca Lusnig, Enrico Martinelli:
Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors. 56-59 - Miltos D. Grammatikakis, Antonis Papagrigoriou, Polydoros Petrakis, George Kornaros:
Non-intrusive NoC DFS for Soft Real-Time Multimedia Applications. 60-63 - Rodrigo Fernández, Hector Posadas, Eugenio Villar:
Early Performance Evaluation of Multi-OS Embedded Platforms Using Native Simulation. 64-67 - Mohamad Hairol Jabbar, Dominique Houzet, Omar Hammami:
Impact of 3D IC on NoC Topologies: A Wire Delay Consideration. 68-72 - Luka B. Daoud, Victor Goulart:
High Performance Bitwise OR Based Submesh Allocation for 2D Mesh-Connected CMPs. 73-77 - Sahar Foroutan, Benny Akesson, Kees Goossens, Frédéric Pétrot:
A General Framework for Average-Case Performance Analysis of Shared Resources. 78-85
DSD-3: Modelling and Verification
- Mikhail Glukhikh, Mikhail J. Moiseev, Sergey I. Salishev:
A Static Analysis Approach for Verification of Synchronization Correctness of SystemC Designs. 89-96 - Vidya V. Parappurath, Jeroen Voeten, Kees C. Kotterink:
Calibration Error Bound Estimation in Performance Modeling. 97-102 - Parthasarathy Ravishankar, Samar Abdi:
pCache: An Observable L1 Data Cache Model for FPGA Prototyping of Embedded Systems. 103-110 - Sergey Ostroumov, Leonidas Tsiopoulos, Kaisa Sere, Juha Plosila:
Generation of Structural VHDL Code with Library Components from Formal Event-B Models. 111-118
FTDSD 1: Fault Tolerance in Digital System Design
- Thomas Polzer, Andreas Steininger:
Digital Late-Transition Metastability Simulation Model. 121-128 - Alexander Uhl, Jürgen Becker:
Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms. 129-135 - Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls:
Identifying NBTI-Critical Paths in Nanoscale Logic. 136-141 - Christoph Lenzen, Matthias Függer, Markus Hofstatter, Ulrich Schmid:
Efficient Construction of Global Time in SoCs Despite Arbitrary Faults. 142-151
FDR: Flexible Digital Radio
- Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet:
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. 155-162 - Vincent Berg, Jean-Baptiste Dore, Dominique Noguet:
A Flexible Radio Transmitter for TVWS Based on FBMC. 163-167 - Carlo Condo, Amer Baghdadi, Guido Masera:
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. 168-174 - José Rodríguez-Piñeiro, José Antonio García-Naya, Angel Carro-Lagoa, Luis Castedo:
A Testbed for Evaluating LTE in High-Speed Trains. 175-182
DSD-4: Reconfigurable Computing 1
- Hasan Erdem Yantir, Salih Bayar, Arda Yurdakul:
Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs. 185-192 - Florian Aschauer, Walter Stechele, Johannes Treis:
Dynamic Noise Estimation Approach for X-Ray Detectors on FPGAs. 193-200 - Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau:
A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints. 201-208 - Teodor Ivan, El Mostapha Aboulhamid:
An Efficient Hardware Implementation of a SAT Problem Solver on FPGA. 209-216
FTDSD 2: Fault Tolerance in Digital System Design
- Rishad A. Shafik, Gerard K. Rauwerda, Jordy Potman, Kim Sunesen, Dhiraj K. Pradhan, Jimson Mathew, Ioannis Sourdis:
Software Modification Aided Transient Error Tolerance for Embedded Systems. 219-226 - Lukas Miculka, Martin Straka, Zdenek Kotásek:
Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area. 227-234 - Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus:
Virtual TMR Schemes Combining Fault Tolerance and Self Repair. 235-242 - Peter Raab, Stanislav Racek, Stefan Krämer, Jürgen Mottok:
Data Flow Analysis of Software Executed by Unreliable Hardware. 243-249
EPDSD 1: European Projects in Digital System Design
- Nicola Bombieri, Giuliana Drogoudis, Giuliana Gangemi, Renaud Gillon, Enrico Macii, Massimo Poncino, Salvatore Rinaudo, Francesco Stefanni, Dimitrios Trachanis, Mark van Helvoort:
SMAC: Smart Systems Co-design. 253-259 - Salvador Trujillo, Alfons Crespo, Alejandro Alonso:
MultiPARTES: Multicore Virtualization for Mixed-Criticality Systems. 260-265 - Miodrag R. Temerinac, Ivan Kastelan, Karolj Skala, Branka Medved Rogina, Leonhard M. Reindl, Florent Souvestre, Margarita Anastassova, Roman Szewczyk, Jan Piwinski, Jorge R. López Benito, Enara Artetxe González, Nikola Teslic, Vlado Sruk, Moshe Barak:
E2LP: A Unified Embedded Engineering Learning Platform. 266-271 - Marco Solinas, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Luján, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stéphane Zuckerman, Roberto Giorgi:
The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. 272-279
Poster Session 2
- Juan Núñez, Maria J. Avedillo, José M. Quintana:
Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. 280-283 - Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. 284-287 - Ashfaq Ahmed, Muhammad Usman Shahid, Maurizio Martina, Enrico Magli, Guido Masera:
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding. 288-292 - Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi:
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. 293-296 - Muhammad Awais Aslam, Shashi Kumar, Rickard Holsmark:
An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC Platforms. 297-300 - Filippos Pirpilidis, Paris Kitsos, Nicolas Sklavos:
An Efficient FPGA-Based Architecture of Skein for Simple Hashing and MAC Function. 301-304 - Tamas Györfi, Octavian Cret, Zalan Borsos:
Implementing Modular FFTs in FPGAs - A Basic Block for Lattice-Based Cryptography. 305-308
DSD-5: NoC Routing
- Changlin Chen, Sorin Dan Cotofana:
An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs. 311-318 - Evangelia Kasapaki, Jens Sparsø, Rasmus Bo Sørensen, Kees Goossens:
Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip. 319-326 - Mohammad Mirzaei, Mahdi Mosaffa, Siamak Mohammadi, Jelena Trajkovic:
Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth Approaches. 327-334
AHSA 1: Architectures and Hardware for Security Applications
- Norbert Druml, Manuel Menghin, Daniel Kroisleitner, Christian Steger, Reinhold Weiss, Armin Krieg, Holger Bock, Josef Haid:
Emulation-Based Fault Effect Analysis for Resource Constrained, Secure, and Dependable Systems. 337-344 - Guilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine:
Electromagnetic Analysis on RSA Algorithm Based on RNS. 345-352 - Shohreh Sharif Mansouri, Elena Dubrova:
Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures. 353-359
EPDSD 2: European Projects in Digital System Design
- Theo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, João Fernandes, Pavel G. Zaykov, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Ian Broster, Nick Lay, David George, Eduardo Quiñones, Milos Panic, Jaume Abella, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka:
parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. 363-370 - Hector Posadas, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Antoniu Pop, Nhat Minh Lê, Adrien Guatto, Mihai T. Lazarescu, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Daniel Calvo, Eduardo de las Heras:
EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications. 371-378 - George Goulas, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos, Oliver Oey, Timo Stripf, Thomas Bruckschlögl, Jürgen Becker, Ali El Moussawi, Maxime Naullet, Tomofumi Yuki:
Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems. 379-386
DSD-6: Optimization and Performance
- Nasim Farahini, Ahmed Hemani, Kolin Paul:
Distributed Runtime Computation of Constraints for Multiple Inner Loops. 389-395 - Carlo Brandolese, William Fornaciari, Luigi Rucco:
A Formal Model for Optimal Autonomous Task Hibernation in Constrained Embedded Systems. 396-403 - Fatemeh Kashfi, Jeff Draper:
Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICs. 404-411
DSD-7: Video
- Pedro P. Carballo, Omar Espino, Romén Neris, Pedro Hernandez-Fernandez, Tomasz Szydzik, Antonio Núñez:
Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology. 415-422 - Grzegorz Pastuszak, Maciej Trochimiuk:
Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder. 423-428 - Andrzej Abramowski, Grzegorz Pastuszak:
A Novel Intra Prediction Architecture for the Hardware HEVC Encoder. 429-436
DTDS 1: Dependability and Testing of Digital Systems
- Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler:
Minimal Stimuli Generation in Simulation-Based Verification. 439-444 - Jiri Balcarek, Petr Fiser, Jan Schmidt:
Simulation and SAT Based ATPG for Compressed Test Generation. 445-452 - Martin Keim, Tom Waayers, Richard Morren, Friedrich Hapke, Rene Krenz-Baath:
Industrial Application of IEEE P1687 for an Automotive Product. 453-461
Poster Session 3
- Yaroub Elloumi, Mohamed Akil, Mohamed Bedoui Hedi:
Execution Time and Code Size Optimization Using Multidimensional Retiming and Loop Striping. 462-466 - Pablo Peñil, Pablo Sánchez Espeso, David de la Fuente, Jesús Barba, Juan Carlos López:
UML/MARTE Methodology for Automatic SystemC Code Generation of Openmax Multimedia Applications. 467-470 - Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal:
An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors. 471-474 - Miroslav Siebert, Elena Gramatová:
Delay Fault Coverage Increasing in Digital Circuits. 475-478 - Konstantin O. Petrosyants, Igor A. Kharitonov:
Account for Radiation Effects in Signal Integrity Analysis of PCB Digital Systems. 479-482 - Karim Tobich, Philippe Maurine, Pierre-Yvan Liardet, Mathieu Lisart, Thomas Ordas:
Voltage Spikes on the Substrate to Obtain Timing Faults. 483-486
DSD-8: SoC & NoC 2
- Majed ValadBeigi, Farshad Safaei, Bahareh Pourshirazi:
An Energy-Efficient Reconfigurable NoC Architecture with RF-Interconnects. 489-496 - Miltos D. Grammatikakis, Antonis Papagrigoriou, Polydoros Petrakis, George Kornaros:
Monitoring-Aware Virtual Platform Prototype of Heterogeneous NoC-Based Multicore SoCs. 497-504 - Giuseppe Ascia, Maurizio Palesi, Vincenzo Catania:
An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip. 505-512 - Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung:
Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-Time Mapping for Heterogeneous MPSoCs. 513-521
DSD-9: Reconfigurable Computing 2
- Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. 525-534 - Florian Aschauer, Walter Stechele, Johannes Treis:
FPGA Based Real-Time Data Processing DAQ System for the Mercury Imaging X-Ray Spectrometer. 535-542 - Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys:
Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations. 543-550 - Adrian Willenbücher, Klaus Schneider:
Automatic Hard Block Inference on FPGAs. 551-557
DTDS 2: Dependability and Testing of Digital Systems
- Martin Danhel, Hana Kubátová, Radek Dobias:
Predictive Analysis of Mission Critical Systems Dependability. 561-566 - Bibhas Ghoshal, Indranil Sengupta:
A Distributed BIST Scheme for NoC-Based Memory Cores. 567-574 - Muhammad Aamir Khan, Hans G. Kerkhoff:
The Essence of Reliability Estimation during Operational Life for Achieving High System Dependability. 575-581 - Jannis Stoppe, Robert Wille, Rolf Drechsler:
Cone of Influence Analysis at the Electronic System Level Using Machine Learning. 582-587
MSDA 1: Multicore Systems: Design and Applications
- Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. 591-597 - Emilio Castillo, Cristobal Camarero, Esteban Stafford, Fernando Vallejo, José Luis Bosque, Ramón Beivide:
Advanced Switching Mechanisms for Forthcoming On-Chip Networks. 598-605
AHSA 2: Architectures and Hardware for Security Applications
- Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Laser-Induced Fault Simulation. 609-614 - Florent Lozach, Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger:
FPGA Design of an Open-Loop True Random Number Generator. 615-622
MRES 1: Management and Reconfiguration of Embedded Systems
- Daniele Bortolotti, Andrea Bartolini, Luca Benini:
An Ambient Temperature Variation Tolerance Scheme for an Ultra Low Power Shared-L1 Processor Cluster. 625-632 - Teresa Cervero, Julio Dondo, Ana Gomez, Xerach Peña, Sebastián López, Fernando Rincón Calle, Roberto Sarmiento, Juan Carlos López:
A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems. 633-640
Poster Session 4
- Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay:
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic. 641-644 - Filip Stepánek, Jirí Bucek, Martin Novotný:
Differential Power Analysis under Constrained Budget: Low Cost Education of Hackers. 645-648 - Miguel Morales-Sandoval, Arturo Diaz-Perez:
Compact FPGA-Based Hardware Architectures for GF(2^m) Multipliers. 649-652 - Rajendra S. Katti, Rucha Sule:
MISRs for Fast Authentication of Long Messages. 653-657 - Zahra Jeddi, Esmaeil Amini, Magdy A. Bayoumi:
A Novel Authenticated Encryption Algorithm for RFID Systems. 658-661 - Amr Al-Anwar, Yousra Alkabani, M. Watheq El-Kharashi, Hassan Bedour:
Hardware Trojan Protection for Third Party IPs. 662-665 - Julián Caba, Julio Dondo, Fernando Rincón, Jesús Barba, Juan Carlos López:
Development Flow for FPGA-Based Scalable Reconfigurable Systems. 666-669
DSD-10: Applications
- Paolo Motto Ros, Marco Crepaldi, Alberto Bonanno, Danilo Demarchi:
Wireless Multi-channel Quasi-digital Tactile Sensing Glove-Based System. 673-680 - Muhammad Imran, Naeem Ahmad, Khursheed Khursheed, Mattias O'Nils, Najeem Lawal:
Low Complexity Background Subtraction for Wireless Vision Sensor Node. 681-688 - Kristin Scholfield, Tom Chen:
A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications. 689-694
AHSA 3: Architectures and Hardware for Security Applications
- Bilal Habib, Kris Gaj, Jens-Peter Kaps:
FPGA PUF Based on Programmable LUT Delays. 697-704 - Johann Ertl, Thomas Plos, Martin Feldhofer, Norbert Felber, Luca Henzen:
A Security-Enhanced UHF RFID Tag Chip. 705-712 - Ming Liu, Shohreh Sharif Mansouri, Elena Dubrova:
A Faster Shift Register Alternative to Filter Generators. 713-718
MRES 2: Management and Reconfiguration of Embedded Systems
- Daniel Gregorek, Christof Osewold, Alberto García Ortiz:
A Scalable Hardware Implementation of a Best-Effort Scheduler for Multicore Processors. 721-727 - Carlos Benito, Pablo Ituero, Marisa López-Vallejo:
A Low-Area Reference-Free Power Supply Sensor. 728-733 - Alice M. Tokarnia, Emerson P. Cruz:
Scenario Patterns and Trace-Based Temporal Verification of Reactive Embedded Systems. 734-741
DSD-11: Adaptive Communication Techniques
- Yuan Fang, Ling Chen, Ashok Jaiswal, Klaus Hofmann, Peter Gregorius:
Adaptive Equalizer Training for High-Speed Low-Power Communication Systems. 745-751 - Ashok Jaiswal, Yuan Fang, Peter Gregorius, Klaus Hofmann:
Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems. 752-758
DSD-12: SoC & NoC 3
- Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf:
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. 761-768 - Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny:
Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip. 769-776
DCPS 1: Design of Cyber-physical Systems
- A. A. Nacci, Matteo Mazzucchelli, Martina Maggio, Alessandra Bonetto, Donatella Sciuto, Marco D. Santambrogio:
Morphone.OS: Context-Awareness in Everyday Life. 779-786 - Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia:
UML-Based Modeling and Simulation of Environmental Effects in Networked Embedded Systems. 787-794
Poster Session 5
- Matthias Hartmann, Praveen Raghavan, Liesbet Van der Perre, Prashant Agrawal, Wim Dehaene:
Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design. 795-798 - Angela Souto Vieites, Roberto R. Osorio:
Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks. 799-802 - Elisa Marenzi, Gian Mario Bertolotti, Francesco Leporati, Giovanni Danese:
Capacitive Sensors Matrix for Interface Pressure Measurement in Clinical, Ergonomic and Automotive Environments. 803-806 - Sara Rampazzi, Giovanni Danese, Lucia Fornasari, Francesco Leporati, Franco Marabelli, Nelson Nazzicari, Armand Valsesia:
Lab on Chip: Portable Optical Device for On-site Multi-parametric Analysis. 807-810 - Raymond Frijns, A. L. J. Kamp, Sander Stuijk, Jeroen Voeten, M. Bontekoe, K. J. A. Gemei, Henk Corporaal:
Dataflow-Based Multi-ASIP Platform Approach for Digital Control Applications. 811-814 - Alberto Casagrande, Tommaso Dreossi:
pyHybrid Analysis: A Package for Semantics Analysis of Hybrid Systems. 815-818
DSD-13: System Hardware and Embedded Software
- Mehmet Ali Arslan, Krzysztof Kuchcinski:
Instruction Selection and Scheduling for DSP Kernels on Custom Architectures. 821-828 - Filipe Sousa, Francis Anghinolfi, João Canas Ferreira:
Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques. 829-835 - Amit Kumar Singh, Anup Das, Akash Kumar:
RAPIDITAS: RAPId Design-Space-Exploration Incorporating Trace-Based Analysis and Simulation. 836-843 - Wei Song, Jim D. Garside:
Automatic Controller Detection for Large Scale RTL Designs. 844-851
FTDSD 3: Fault Tolerance in Digital System Design
- Stefan Weidling, Egor S. Sogomonyan, Michael Gössel:
Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection. 855-862 - Muhammad Ali Akbar, Jeong-A Lee:
Self-Checking Carry Select Adder with Fault Localization. 863-869 - Zahid Ali Siddiqui, Park Hui-Jong, Jeong-A Lee:
Area-Time Efficient Self-Checking ALU Based on Scalable Error Detection Coding. 870-877
EEES: Energy-Efficient Embedded Systems
- Gang Chen, Kai Huang, Jia Huang, Christian Buckl, Alois C. Knoll:
Effective Online Power Management with Adaptive Interplay of DVS and DPM for Embedded Real-Time System. 881-889 - Yahia Benmoussa, Jalil Boukhobza, Eric Senn, Djamel Benazzouz:
Energy Consumption Modeling of H.264/AVC Video Decoding for GPP and DSP. 890-897 - Norbert Druml, Manuel Menghin, Tobias Rauter, Christian Steger, Reinhold Weiss, Christian Bachmann, Holger Bock, Josef Haid:
Power and Thermal Fault Effect Exploration Framework for Reader/Smart Card Designs. 898-906 - Manuel Menghin, Norbert Druml, Manuel Trebo Fioriello, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid:
PtNBridge - A Power-Aware and Trustworthy Near Field Communication Bridge to Embedded Systems. 907-914
DSD-14: Digital System Design
- Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
Master-Slave Control Structure for Massively Parallel System on Chip. 917-924 - Mostafa Said, Farhad Mehdipour, Mohamed El-Sayed:
Improving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon Vias. 925-932 - Matheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost:
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. 933-940 - Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania:
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip. 941-944
AHSA 4: Architectures and Hardware for Security Applications
- Rajesh Velegalati, Kinjal Shah, Jens-Peter Kaps:
Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling Techniques. 947-954 - Yarkin Doröz, Erdinç Öztürk, Berk Sunar:
Evaluating the Hardware Performance of a Million-Bit Multiplier. 955-962 - Souvik Kolay, Sagar Khurana, Anupam Sadhukhan, Chester Rebeiro, Debdeep Mukhopadhyay:
PERMS: A Bit Permutation Instruction for Accelerating Software Cryptography. 963-968 - Ghada Y. Abozaid, Ahmed El-Mahdy, Yasutaka Wada:
A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption. 969-975
DCPS 2: Design of Cyber-physical Systems
- Shreya Adyanthaya, Marc Geilen, Twan Basten, Ramon R. H. Schiffelers, Bart D. Theelen, Jeroen Voeten:
Fast Multiprocessor Scheduling with Fixed Task Binding of Large Scale Industrial Cyber Physical Systems. 979-988 - Fernando Herrera, Seyed-Hosein Attarzadeh-Niaki, Ingo Sander:
Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems. 989-996 - Giovanni Lorenzi, Davide Quaglia, Riccardo Muradore, Paolo Fiorini:
Passivity-Based Control over Differentiated-Services Packet Networks. 997-1004 - Marco Crepaldi, Paolo Motto Ros, Danilo Demarchi, John L. Buckley, Brendan O'Flynn, Davide Quaglia:
A Physical-Aware Abstraction Flow for Efficient Design-Space Exploration of a Wireless Body Area Network Application. 1005-1012
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