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ORCIDIEEE Journal of Solid-State Circuits, Volume 29
Volume 29, Number 1, January 1994
- Yoshiki Tsujihashi, Hisashi Matsumoto, Hidekatsu Nishimaki, Atsushi Miyanishi, Hiroomi Nakao, Osamu Kitada, Shuhei Iwade, Shinpei Kayano, Masayoshi Sakao:
A high-density data-path generator with stretchable cells. 2-8 - Yohji Watanabe, Nobuo Nakamura, Shigeyoshi Watanabe:
Offset compensating bit-line sensing scheme for high density DRAM's. 9-13 - Graham A. Jullien, William C. Miller, Roger Grondin, Lino Del Pup, Sami S. Bizzan, David Zhang
:
Dynamic computational blocks for bit-level systolic arrays. 14-22 - Hans Hageraats, Pieter W. Hooijmans, Mark Tomesen:
A new wide-band input compensation for packaged analog and digital multigigabit IC's. 23-30 - Khaled M. Sharaf, Mohamed I. Elmasry:
An accurate analytical propagation delay model for high-speed CML bipolar circuits. 31-45 - Katsuji Kimura:
A bipolar four-quadrant analog quarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges. 46-55 - Jon S. Martens, Aleksandar Pance, Kookrin Char, Marie E. Johansson, Stephen R. Whiteley, Joel R. Wendt, Vincent M. Hietala, Tom A. Plut, Carol I. H. Ashby, Shang Y. Hou, Julia M. Phillips:
High-temperature superconducting shift registers operating at up to 100 GHz. 56-62 - Wen-Chung S. Wu, Ward J. Helms, Jay A. Kuhn, Bruce E. Byrkett:
Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges. 63-66 - Avner Efendovich, Yachin Afek, Coby Sella, Zeev Bikowsky:
Multifrequency zero-jitter delay-locked loop. 67-70 - Jeff Conger, Andrzej Peczalski, Michael S. Shur:
Modeling frequency dependence of GaAs MESFET characteristics. 71-76 - C. C. Lo, G. P. Li, J. H. Mulligan:
An approximation to the factor K in the Toh-Ko-Meyer MOS engineering model. 77-78
Volume 29, Number 2, February 1994
- Muhammad E. S. Elrabaa, Michael S. Obrecht, Mohamed I. Elmasry:
Novel low-voltage low-power full-swing BiCMOS circuits. 86-94 - K. Wayne Current:
Current-mode CMOS multiple-valued logic circuits. 95-107 - Cemal T. Dikmen, Numan S. Dogan, Mohamed A. Osman:
DC modeling and characterization of AlGaAs/GaAs heterojunction bipolar transistors for high-temperature applications. 108-116 - Alan Y. Kwentus, Hing-Tsun Hung, Alan N. Willson Jr.:
An architecture for high-performance/small-area multipliers for use in digital filtering applications. 117-121 - Bhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl:
Short channel models and scaling limits of SOI and bulk MOSFETs. 122-125 - Attilio J. Rainal:
Eliminating inductive noise of external chip interconnections. 126-129 - Richard E. Vallee, Ezz I. El-Masr:
A very high-frequency CMOS complementary folded cascode amplifier. 130-133 - Thomas C. Banwell:
Simple precision bias circuit for medium-power amplifiers. 134-137 - Francesco Forti, Michael E. Wright:
Measurement of MOS current mismatch in the weak inversion region. 138-142 - Wim Van Petegem, Ben Geeraerts, Willy Sansen, Benny Graindourze:
Electrothermal simulation and design of integrated circuits. 143-146 - Massimo Lanzoni, Luciano Briozzo, Bruno Riccò:
A novel approach to controlled programming of tunnel-based floating-gate MOSFETs. 147-150 - N. Scheinberg, R. Michels:
A monolithic GaAs low power L-band successive detection logarithmic amplifier. 151-154 - Nils Hedenstiema, Kjell O. Jeppson:
Comments on the optimum CMOS tapered buffer problem. 155-158 - Laszlo Gal:
Reply to "Comments on the optimum CMOS tapered buffer problem". 158-159
Volume 29, Number 3, March 1994
- Yannis P. Tsividis:
Integrated continuous-time filter design - an overview. 166-176 - Rick A. Philpott, Robert A. Kertis, Ray Richetta, Timothy J. Schmerbeck, Donald J. Schulte:
A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection. 177-184 - Barry Thompson, Hae-Seung Lee, Lawrence M. DeVito:
A 300-MHz BiCMOS serial data transceiver. 185-192 - Louis A. Williams, Bruce A. Wooley:
A third-order sigma-delta modulator with extended dynamic range. 193-202 - Rajesh H. Zele, David J. Allstot:
Low-voltage fully differential switched-current filters. 203-209 - Yannis P. Tsividis, Ken Suyama:
MOSFET modeling for analog circuit CAD: problems and prospects. 210-216 - Richard J. Trihy, Ronald A. Rohrer:
A switched capacitor circuit simulator: AWEswit. 217-225 - Balsha R. Stanisic, Nishath K. Verghese, Rob A. Rutenbar, L. Richard Carley, David J. Allstot:
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis. 226-238 - Theodore L. Tewksbury, Hae-Seung Lee:
Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs. 239-252 - Khandker N. Quader, Eric R. Minami, Wei-Jen Huang, Ping K. Ko, Chenming Hu:
Hot-carrier-reliability design guidelines for CMOS logic circuits. 253-262 - Steven D. Millman, John M. Acken:
Special applications of the voting model for bridging faults. 263-270 - Dejan Mijuskovic, Martin Bayer, Thecla Chomicz, Nitin Garg, Frederick James, Philip McEntarfer, Jeff Porter:
Cell-based fully integrated CMOS frequency synthesizers. 271-279 - Tetsuro Kawata, Kenichi Kawauchi, Nobuaki Miyakawa, Ichiro Kawazome, Hiromi Yasumatsu, Susumu Haga, Masaya Takenaka:
An outline font rendering processor with an embedded RISC CPU for high-speed hint processing. 280-289 - Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada:
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. 290-297 - Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh:
3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. 298-302 - Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm. 303-307 - Kiyohiro Furutani, Hiroshi Miyamoto, Yoshikazu Morooka, M. Suwa, Hideyuki Ozaki:
An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM. 308-310 - Katsuhiko Ohsaki, Noriaki Asamoto, Shunichi Takagaki:
A single poly EEPROM cell structure for use in standard CMOS processes. 311-316 - Laurent Lemaitre, Marek J. Patyra, Daniel Mlynek:
Analysis and design of CMOS fuzzy logic controller in current mode. 317-322 - Norman J. Elias:
Acceptance sampling: an efficient, accurate method for estimating and optimizing parametric yield. 323-327 - Joongho Choi, Bing J. Sheu, Oscal T.-C. Chen:
A monolithic GaAs receiver for optical interconnect systems. 328-331 - Behzad Razavi, Yusuke Ota, Robert G. Swartz:
Design techniques for low-voltage high-speed digital bipolar circuits. 332-339 - C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III:
A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. 340-349 - Robert G. Meyer, William D. Mack:
A 1-GHz BiCMOS RF front-end IC. 350-355 - Samir S. Rofail, Mohamed I. Elmasry:
Schottky merged BiCMOS structures. 356-361 - Kalevi Hyyppä, Klas Ericson:
Low-noise photodiode-amplifier circuit. 362-365 - Joe Staudinger, Mike Golio, Charlie Woodin, Monica C. de Baca:
Considerations for improving the accuracy of large-signal GaAs MESFET models to predict power amplifier circuit performance. 366-373
Volume 29, Number 4, April 1994
- Bryan Ackland:
The role of VLSI in multimedia. 381-388 - Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura:
A 120-MHz BiCMOS superscalar RISC processor. 389-396 - John W. Fattaruso, Shivaling S. Mahant-Shetti, J. Brock Barton:
A fuzzy logic inference processor. 397-402 - Yasuo Unekawa, Tsuguo Kobayashi, Tsukasa Shirotori, Yukihiro Fujimoto, Takayoshi Shimazawa, Kazutaka Nogami, Takehiko Nakao, Kazukiro Sawada, Masataka Matsui, Takayasu Sakurai, Man Kit Tang, William A. Huffman:
A 110-MHz/1-Mb synchronous TagRAM. 403-410 - Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki:
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. 411-418 - Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima:
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. 419-425 - Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe:
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. 426-431 - Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima:
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. 432-440 - Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango:
Standby/active mode logic for sub-1-V operating ULSI memory. 441-447 - Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa:
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. 448-453 - Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara:
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. 454-460 - Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Kiyomi Naruke, Seiji Yamada, Yoichi Ohshima, Masamitsu Oshikiri, Yohei Hiura, Tomoko Yamane, Kuniyoshi Yoshikawa:
A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. 461-469 - Akira Matsuzawa:
Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment. 470-480 - Robert Adams, Tom Kwan:
A stereo asynchronous digital sample-rate converter for digital audio. 481-488 - Patrick Pai, Asad A. Abidi:
A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels. 489-499 - Gunther M. Haller, Bruce A. Wooley:
A 700-MHz switched-capacitor analog waveform sampling circuit. 500-508 - Hae-Seung Lee:
A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC. 509-515 - Takahiro Miki, Hiroyuki Kouno, Toshio Kumamoto, Yasushi Kinoshita, Takayuki Igarashi, Keisuke Okada:
A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter. 516-522 - Hyun J. Shin:
A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits. 523-528 - Yunho Choi, Myungho Kim, Hyunsoon Jang, Taejin Kim, Seung-hoon Lee, Ho-cheol Lee, Churoo Park, Siyeol Lee, Cheol-soo Kim, Soo-In Cho, Ejaz Haq, J. Karp, Daeje Chin:
16-Mb synchronous DRAM with 125-Mbyte/s data rate. 529-533 - Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki:
An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs. 534-538 - Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi:
Open/folded bit-line arrangement for ultra-high-density DRAM's. 539-542
Volume 29, Number 5, May 1994
- Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi:
High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. 546-550 - Wolfgang Pöhlmann:
A silicon-bipolar amplifier for 10 Gbit/s with 45 dB gain. 551-556 - Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino:
BiCMOS circuit technology for a 704 MHz ATM switch LSI. 557-563 - Tadahiro Kuroda, Yoshinori Sakata, Kenji Matsuo:
Analysis and optimization of BiCMOS gate circuits. 564-571 - Samir S. Rofail:
Low-voltage, low-power BiCMOS digital circuits. 572-579 - Jien-Chung Lo, Shih-Yao Sun, James C. Daly:
A concurrent error detection IC in 2-μm static CMOS logic. 580-584 - Long Yang, Steven D. Draving, Dan E. Mars, Mike R. T. Tan:
A 50 GHz broad-band monolithic GaAs/AlAs resonant tunneling diode trigger circuit. 585-595 - Victor Da Costa, Russel A. Martin:
Amorphous silicon shift register for addressing output drivers. 596-600 - Chong-Gun Yu, Randall L. Geiger:
An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiers. 601-610 - M. J. McNutt, S. LeMarquis, J. L. Dunkley:
Systematic capacitance matching errors and corrective layout procedures. 611-616 - Oscar M. K. Law, C. André T. Salama:
GaAs split phase dynamic logic. 617-622 - Ming-Huei Shieh, Hung Chang Lin:
A multiple-dimensional multiple-state SRAM cell using resonant tunneling diodes. 623-630 - Rajendra Kumar:
NCMOS: a high performance CMOS logic. 631-633 - Dirk Timmermann, Bernold Rix, Helmut Hahn, Bedrich J. Hosticka:
A CMOS floating-point vector-arithmetic unit. 634-639 - P. T. Lai, Y. C. Cheng:
A closed-form delay expression for digital BiCMOS circuits with high-injection effects. 640-643
Volume 29, Number 6, June 1994
- Kjell O. Jeppson:
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay. 646-654 - Patrik Larsson, Christer Svensson:
Noise in digital dynamic CMOS circuits. 655-662 - Dake Liu, Christer Svensson:
Power consumption estimation in CMOS VLSI chips. 663-670 - Mohamed Y. Osman, Mohamed I. Elmasry:
Highly testable design of BiCMOS logic circuits. 671-678 - Brian P. Brandt, Bruce A. Wooley:
A low-power, area-efficient digital filter for decimation and interpolation. 679-687 - Norman Scheinberg, R. Michels, V. Fedoroff, D. Stoffman, K. Li, S. Kent, M. Waight, D. Marz:
A GaAs up converter integrated circuit for a double conversion cable TV "set-top" tuner. 688-692 - Abdellatif Bellaouar, Issam S. Abu-Khater, Mohamed I. Elmasry, A. Chikima:
Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling. 693-700 - Robert G. Meyer, William D. Mack:
A wideband low-noise variable-gain BiCMOS transimpedance amplifier. 701-706 - Marc J. Loinaz, Bruce A. Wooley:
A BiCMOS time interval digitizer based on fully-differential, current-steering circuits. 707-714 - Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki:
A charge recycle refresh for Gb-scale DRAM's in file applications. 715-722 - Patrik Larsson, Christer Svensson:
Impact of clock slope on true single phase clocked (TSPC) CMOS circuits. 723-726 - Hai-Gang Yang, Steve Fluxman, Carlo Reita, Piero Migliorato:
Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers. 727-732 - Dima D. Shulman:
A static memory cell based on the negative resistance of the gate terminal of p-n-p-n devices. 733-736 - Nicholas C. Battersby, Chris Toumazou:
A high-frequency fifth order switched-current bilinear elliptic lowpass filter. 737-740 - Sherif H. K. Embabi, D. E. Brueske, K. Rachamreddy:
A BiCMOS low-power current mode gate. 741-745 - Navin Saxena, James J. Clark:
A four-quadrant CMOS analog multiplier for analog neural networks. 746-749 - Shen-Iuan Liu, Yuh-Shyan Hwang:
CMOS four-quadrant multiplier using bias feedback techniques. 750-752
Volume 29, Number 7, July 1994
- Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi:
Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit. 754-760 - Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Subthreshold-current reduction circuits for multi-gigabit DRAM's. 761-769 - Howard V. Savin, Mary S. Bucknell, Marc D. Spaulding, Thomas B. Maciukenas, W. Kent Fuchs:
Design for concurrent error detection and testability in storage/logic arrays. 770-779 - Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng:
New efficient designs for XOR and XNOR functions on the transistor level. 780-786 - Shayan Zhang, T. S. Kalkur, Steven Lee, Dengyuan Chen:
Analysis of the switching speed of BiCMOS buffer under high current. 787-796 - Shayan Zhang, T. S. Kalkur:
Analysis of BiCMOS buffer for input voltages with finite rise time. 797-807 - Norio Higashisaka, M. Shimada, Akira Ohta, Kenji Hosogi, Y. Tobita, Yasuo Mitsui:
GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's. 808-814 - Michael Möller, Hans-Martin Rein, Horst Wernz:
13 Gb/s Si-bipolar AGC amplifier IC with high gain and wide dynamic range for optical-fiber receivers. 815-822 - Badram Fotouhi:
Optimization of chopper amplifiers for speed and gain. 823-828 - Walter H. Henkels, Wei Hwang:
Large-signal 2T, 1C DRAM cell: signal and layout analysis. 829-832 - Bing Wang, James R. Hellums, Charles G. Sodini:
MOSFET thermal noise modeling for analog integrated circuits. 833-835 - Ching-Te Chuang, Kenneth Chin:
High-speed low-power direct-coupled complementary push-pull ECL circuit. 836-839 - Pasqualino Visocchi, John T. Taylor, Richard Mason, Andrew Betts, David Haigh:
Design and evaluation of a high-precision, fully tunable OTA-C bandpass filter implemented in GaAs MESFET technology. 840-843 - Shen Feng, Dieter Seitzer:
Characterization and improvement of GaAs HEMT analog switches for sampled-data applications. 844-850
Volume 29, Number 8, August 1994
- Guangming Yin, Willy Sansen:
A high-frequency and high-resolution fourth-order ΣΔ A/D converter in BiCMOS technology. 857-865 - Jiren Yuan, Crister Svensson:
A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS. 866-872 - Marcel J. M. Pelgrom, A. C. Jeannet v. Rens, Maarten Vertregt, Marcel B. Dijkstra:
A 25-Ms/s 8-bit CMOS A/D converter for embedded application. 879-886 - Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. 887-894 - Servando Espejo, Ángel Rodríguez-Vázquez, Rafael Domínguez-Castro, John L. Huertas, Edgar Sánchez-Sinencio:
Smart-pixel cellular neural networks in analog current-mode CMOS technology. 895-905 - Michael Tiefenbacher, Peter Caldera, Franz Dielacher, Jörg Hauptmann, Markus Steiner:
A four-channel CMOS codec filter circuit "SICOFI-4". 906-913 - Didier Haspeslagh, Eric Moerman, Zhong Yuan Chang, Johan Haspeslagh:
A 4/7 kHz audio bandwidth selectable digital phone interface (DPI) chip with on-chip analog functions and modem. 914-920 - Ulrich Kleine, Johannes Bieger, Heinrich Seifert:
A low-noise CMOS preamplifier operating at 4.2 K. 921-926 - Alberto Yúfera, Adoración Rueda, José L. Huertas:
Programmable switched-current wave analog filters. 927-935 - Jan Crols, Michiel Steyaert:
Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages. 936-942 - Wouter A. Serdijn, Albert C. van der Woerd, Jan Davidse, Arthur H. M. van Roermund:
A low-voltage low-power fully-integratable automatic gain control for hearing instruments. 943-946 - Christian Olgaard:
A laser control chip combining a power regulator and a 622-Mbit/s modulator. 947-951 - Patrick Wouters, Michel De Cooman, Robert Puers:
A multi-purpose CMOS sensor interface for low-power applications. 952-956 - Roberto Gariboldi, Francesco Pulvirenti:
A monolithic quad line driver for industrial applications. 957-962 - Piero Malcovati, Carlos Azeredo Leme, Paul O'Leary, Franco Maloberti, Henry Baltes:
Smart sensor interface with A/D conversion and programmable calibration. 963-966 - Damien Macq, Paul G. A. Jespers:
A 10-bit pipelined switched-current A/D converter. 967-971 - Bernardo G. Henriques, José E. Franca:
A high-speed programmable CMOS interface system combining D/A conversion and FIR filtering. 972-977 - Wonchan Kim, Joongsik Kih, Gyudong Kim, Sanghun Jung, Gijung Ahn:
An experimental high-density DRAM cell with a built-in gain stage. 978-981 - P. Heim, E. A. Vittoz:
Precise analog synapse for Kohonen feature maps. 982-985 - Jean-Félix Perotto, C. Lamothe, Claude Arm, Christian Piguet, Evert Dijkstra, Stefan Fink, Eduardo Sanchez, J.-P. Wattenhofer, M. Cecchini:
An 8-bit multitask micropower RISC core. 986-991 - N. R. Scales, Peter J. Hicks, A. D. Armitage, P. A. Payne, Q. X. Chen, John V. Hatfield:
A programmable multi-channel CMOS pulser chip to drive ultrasonic array transducers. 992-994 - Zhi-Gong Wang, Manfred Berroth, Ulrich Nowotny, Peter Hofmann, Axel Hiilsmann, Klaus Köhler, Brian Raynor, Joachim Schneider:
7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT's. 995-997 - William Redman-White, Mark Bracey, James Tijou, B. Murray, C. Hopwood:
An analog CMOS front-end for a D2-MAC TV decoder. 998-1001 - A. Sprotte, K. Buckhorst, Werner Brockherde, Bedrich J. Hosticka, D. Bosch:
CMOS magnetic-field sensor system. 1002-1005 - Eckhard Brass, Ulrich Hilleringmann, Klaus Schumacher:
System integration of optical devices and analog CMOS amplifiers. 1006-1010
Volume 29, Number 9, September 1994
- Hans-Martin Rein, Rolf Schmid, Peter Weger, Tony Smith, Thomas Herzog, Rudolf Lachner:
A versatile Si-bipolar driver circuit with high output voltage swing for external and direct laser modulation in 10 Gb/s optical-fiber links. 1014-1021 - Ramon S. Co, James H. Mulligan Jr.:
Optimization of phase-locked loop performance in data recovery systems. 1022-1034 - Germano Nicollini, Pierangelo Confalonieri, Carlo Crippa, Sergio Pernici, Yves Mazoyer, Carlo Dallavalle, Sergio Mariani, Aldo Calloni:
A 5-V CMOS programmable acoustic front-end for ISDN terminals and digital telephone sets. 1035-1045 - Mukund Padmanabhan, Ken Martin:
A CMOS analog multi-sinusoidal phase-locked-loop. 1046-1057 - Ping-Hsing Lu, Chung-Yu Wu, Ming-Kai Tsai:
Design techniques for tunable transresistance-C VHF bandpass filters. 1058-1067 - Eric J. Gerds, Jan Van der Spiegel, Richard Van Berg, Hugh H. Williams, Ludwig G. A. Callewaert, W. Eyckmans, Willy Sansen:
A CMOS time to digital converter IC with 2 level analog CAM. 1068-1076 - S. Nadeem, Charles G. Sodini, Hae-Seung Lee:
16-channel oversampled analog-to-digital converter. 1077-1085 - Takashi Morie, Yoshihito Amemiya:
An all-analog expandable neural network LSI with on-chip backpropagation learning. 1086-1093 - Carlos Galup-Montoro, Márcio C. Schneider, Itamar J. B. Loss:
Series-parallel association of FET's for high gain and high frequency applications. 1094-1101 - Aria Eshraghi, Terri S. Fiez, Kel D. Winters, Thomas R. Fischer:
Design of a new squaring function for the Viterbi algorithm. 1102-1107 - Walter Guggenbühl, Jiandong Di, Josef Goette:
Switched-current memory circuits for high-precision applications. 1108-1116 - Wentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III:
A 250-MHz wave pipelined adder in 2-μm CMOS. 1117-1128 - Crister Svensson, Jiren Yuan:
A 3-level asynchronous protocol for a differential two-wire communication link. 1129-1132 - Katsuji Kimura, Hiroshi Asazawa:
Frequency mixer with a frequency doubler for integrated circuits. 1133-1137 - Albert C. van der Woerd, Wouter A. Serdijn, R. H. van Beynhem, R. J. H. Janse:
Low-power current-mode 0.9-V voltage regulator. 1138-1141 - Jso-Sun Choi, Kwyro Lee:
Design of CMOS tapered buffer for minimum power-delay product. 1142-1145 - Andrew E. Stevens, Gerald A. Miller:
A high-slew integrator for switched-capacitor circuits. 1146-1149 - Sha Ma, Paul D. Franzon:
Energy control and accurate delay estimation in the design of CMOS buffers. 1150-1153 - David Grant, John Taylor, Paul Houselander:
Design, implementation and evaluation of a high-speed integrated Hamming neural classifier. 1154-1157
Volume 29, Number 10, October 1994
- Doug Smith, Mike Koen, Arthur F. Witulski:
Evolution of high-speed operational amplifier architectures. 1166-1179 - Douglas Mercer:
A 16-b D/A converter with increased spurious free dynamic range. 1180-1185 - Robin Shields, Robert A. Pease:
A dual high-current high-voltage driver. 1186-1190 - Shayan Zhang, T. S. Kalkur, Steven Lee, Lori Gatza:
A delay model and optimization method of a low-power BiCMOS logic circuit. 1191-1199 - Hisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko:
A voltage compensated series-gate bipolar circuit operating at sub-2 V. 1200-1205 - Tim Seneff, Lynelle McKay, Kurt Sakamoto, Neil Tracht:
A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler. 1206-1211 - Kuntal Joardar:
A simple approach to modeling cross-talk in integrated circuits. 1212-1219 - Leo C. N. de Vreede, Henk C. de Graaff, G. A. M. Hurkx, Joseph L. Tauritz, Roel G. F. Baets:
A figure of merit for the high-frequency noise behavior of bipolar transistors. 1220-1226 - Hongxia Xia, Martin C. Lefebvre, David Vinke:
Optimization-based placement algorithm for BiCMOS leaf cell generation. 1227-1237 - Kevin W. Kobayashi, Liem T. Tran, Stacey Bui, Aaron K. Oki, Dwight C. Streit, Mark Rosen:
InAlAs/InGaAs HBT X-band double-balanced upconverter. 1238-1243 - Werner Baumberger:
A single-chip image rejecting receiver for the 2.44 GHz band using commercial GaAs-MESFET-technology. 1244-1249 - Masahiro Maeda, Masaaki Nishijima, Hiroyasu Takehara, Chinatsu Adachi, Hiromasa Fujimoto, Osamu Ishikawa:
A 3.5 V, 1.3 W GaAs power multi-chip IC for cellular phones. 1250-1256 - Kevin W. Kobayashi, Kwan T. Ip, Aaron K. Oki, Donald K. Umemoto, Sahimwn Claxton, Matt Pope, Jerry Wiltz:
GaAs HBT 0.75-5 GHz multifunctional microwave-analog variable gain amplifier. 1257-1261 - Hisanori Uda, Takashi Yamada, Tetsuro Sawai, Kaon Nogawa, Yasoo Harada:
High-performance GaAs switch IC's fabricated using MESFET's with two kinds of pinch-off voltages and a symmetrical pattern configuration. 1262-1269 - Ajay Chandna, Richard B. Brown:
An asynchronous GaAs MESFET static RAM using a new current mirror memory cell. 1270-1276 - Jesper Riishøj, Torben Nørskov Nielsen, Ulrik Gliese:
A 4 Gb/s 2-level to 2 Gsymbol/s 4-level converter GaAs IC for semiconductor optical amplifier QPSK modulators. 1277-1281 - Richard X. Gu, Mohamed I. Elmasry:
High-speed dynamic reference voltage (DRV) CMOS/ECL interface circuits. 1282-1287 - Bedabrata Pain, Eric R. Fossum:
A current memory cell with switch feedthrough reduction by error feedback. 1288-1290 - Christopher Donald Nilson, Robert B. Darling, Robert B. Pinter:
Shunting neural network photodetector arrays in analog CMOS. 1291-1296 - Morteza Vadipour:
Optimum degeneration for minimum mismatch in bipolar current sources. 1297-1300
Volume 29, Number 11, November 1994
- Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara:
An experimental 256-Mb DRAM with boosted sense-ground scheme. 1303-1309 - Hisakazu Kotani, Hironori Akamatsu, Yasushi Naito, Toyokazu Fujii, Tohru Iwata, Toshiaki Tsuji, Yutaka Itoh, Norisato Shimizu, Junji Hirase, Yoshiyuki Shibata, Kazuhiro Yamashita, Takashi Hori, Tsutomu Fujita:
A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures. 1310-1316 - Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. 1317-1322 - Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara:
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. 1323-1329 - Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi:
A 32-bank 256-Mb DRAM with cache and TAG. 1330-1335 - Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina:
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. 1336-1343 - Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda:
A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates. 1344-1352 - Toshio Sunaga:
A 30-ns cycle time 4-Mb mask ROM. 1353-1358 - Emestina Chioffi, Franco Maloberti, Gianmarco Marchesi, Guido Torelli:
High-speed, low-switching noise CMOS memory data output buffer. 1359-1365 - Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara:
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. 1366-1373 - Shu-Yuan Chin, Chung-Yu Wu:
A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources. 1374-1380 - William C. Black, Douglas N. Stephens:
CMOS chip for invasive ultrasound imaging. 1381-1387 - Marius Goldenberg, Russell Croman, Terri S. Fiez:
Accurate SI filters using RGC integrators. 1388-1395 - In-Yeol Lee, Gyudong Kim, Wonchan Kim:
Exponential curvature-compensated BiCMOS bandgap references. 1396-1403 - Domine M. W. Leenaerts, Arjan J. Leeuwenburgh, G. G. Persoon:
A high-performance SI memory cell. 1404-1407
Volume 29, Number 12, December 1994
- Anantha P. Chandrakasan, Andrew Burstein, Robert W. Brodersen:
A low-power chipset for a portable multimedia I/O terminal. 1415-1428 - Kees van Berkel, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij:
A fully asynchronous low-power error corrector for the DCC player. 1429-1439 - Gianfranco Gerosa, Sonya Gary, Carl Dietz, Dac Pham, Kathy Hoover, Jose Alvarez, Hector Sanchez, Pete Ippolito, Tai Ngo, Suzanne Litch, Jim Eno, Jim Golab, Neil Vanderschaaf, Jim Kahle:
A 2.2 W, 80 MHz superscalar RISC microprocessor. 1440-1454 - Robert F. Krick, Lawrence T. Clark, Daniel J. Deleganes, Keng L. Wong, Roshan Fernando, Goutam Debnath, Jashojiban Banik:
A 150 MHz 0.6 μm BiCMOS superscalar microprocessor. 1455-1463 - Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada:
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. 1464-1473 - Masaki Toyokura, Hisashi Kodama, Eiji Miyagoshi, Koyoshi Okamoto, Masahiro Gion, Takayuki Minemaru, Akihiko Ohtani, Toshiyuki Araki, Hiroshi Takeno, Toshihide Akiyama, Brent Wilson, Kunitoshi Aono:
A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC. 1474-1481 - Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai:
A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. 1482-1490 - Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa:
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM. 1491-1496 - Ruud G. H. Eschauzier, Ron Hogervorst, Johan H. Huijsing:
A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF. 1497-1504 - Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, Johan H. Huijsing:
A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries. 1505-1513 - Tapani Ritoniemi, Eero Pajarre, Seppo Ingalsuo, Timo Husu, Ville Eerola, Tapio Saramiiki:
A stereo audio sigma-delta A/D-converter. 1514-1523 - Yasuyuki Matsuya, Junzo Yamada:
1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping. 1524-1530 - Masao Ito, Takahiro Miki, Shiro Hosotani, Toshio Kumamoto, Yukihiro Yamashita, Masaki Kijima, Takashi Okuda, Keisuke Okada:
A 10 bit 20 MS/s 3 V supply CMOS A/D converter. 1531-1536 - Tsugumichi Shibata, Shunji Kimura, Hideaki Kimura, Yuhki Imai, Yohtaro Umeda, Yukio Akazawa:
A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module. 1537-1544 - David Reynolds:
A 320 MHz CMOS triple 8 bit DAC with on-chip PLL and hardware cursor. 1545-1551 - Mark Ingels, Geert Van der Plas, Jan Crols, Michiel Steyaert:
A CMOS 18 THzΩ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links. 1552-1559 - Behzad Razavi, JanMye James Sung:
A 6 GHz 68 mW BiCMOS phase-locked loop. 1560-1565 - Noboru Ishihara, Yukio Akazawa:
A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique. 1566-1571 - Ansgar Pottbacker, Ulrich Langmann:
An 8 GHz silicon bipolar clock-recovery and data-regenerator IC. 1572-1576 - Masaaki Soda, Hiroshi Tezuka, Fumihiko Sato, Takasuke Hashimoto, Satoshi Nakamura, Tom Tatsumi, Tetsuyuki Suzaki, Tsutomu Tashiro:
Si-analog IC's for 20 Gb/s optical receiver. 1577-1582 - Toshiki Seshita, Yoshiko Ikeda, Hirotsugu Wakimoto, Kenji Ishida, Toshiyuki Terada, Tokuhiko Matsunaga, Takashi Suzuki, Yoshiaki Kitaura, Naotaka Uchitomi:
A 20 GHz 8 bit multiplexer IC implemented with 0.5 μm WNx/W-gate GaAs MESFET's. 1583-1588 - Hans W. Klein, Moises E. Robinson:
A 0.8nV/⎷Hz CMOS preamplifier for IC-magneto-resistive read elements. 1589-1595 - Davy Choi, Richard Pierson, Fredrick Trafton, Benjamin Sheahan, Venugopal Gopinathan, Glenn Mayfield, Indumini Ranmuthu, Srinivasan Venkatraman, Vivek Pawar, Owen Lee, William Giolma, William Krenik, William Abbott, Ken Johnson:
An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel. 1596-1605 - Gregory T. Uehara, Paul R. Gray:
A 100 MHz A/D interface for PRML magnetic disk read channels. 1606-1613 - Charles Chien, Rajeev Jain, Etan G. Cohen, Henry Samueli:
A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 μm CMOS. 1614-1623
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