Article

Multi-Core to the Masses

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Justin RattnerAuthors Info & Claims

PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques

Page 3

https://doi.org/10.1109/PACT.2005.31

Published: 17 September 2005 Publication History

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Arge LGoodrich MNelson MSitchinava NMeyer auf der Heide FShavit N(2008)Fundamental parallel algorithms for private-cache chip multiprocessorsProceedings of the twentieth annual symposium on Parallelism in algorithms and architectures10.1145/1378533.1378573(197-206)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1378533.1378573
Golander AWeiss S(2008)Hiding the misprediction penalty of a resource-efficient high-performance processorACM Transactions on Architecture and Code Optimization10.1145/1328195.13282014:4(1-32)Online publication date: 30-Jan-2008
https://dl.acm.org/doi/10.1145/1328195.1328201
Gabor RWeiss SMendelson A(2007)Fairness enforcement in switch on event multithreadingACM Transactions on Architecture and Code Optimization10.1145/1275937.12759394:3(15-es)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1145/1275937.1275939
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Index Terms

Multi-Core to the Masses
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Hardware validation

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Boundary element quadrature schemes for multi- and many-core architectures

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PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques

September 2005

350 pages

ISBN:076952429X

Publisher

IEEE Computer Society

United States

Publication History

Published: 17 September 2005

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Overall Acceptance Rate 121 of 471 submissions, 26%

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Arge LGoodrich MNelson MSitchinava NMeyer auf der Heide FShavit N(2008)Fundamental parallel algorithms for private-cache chip multiprocessorsProceedings of the twentieth annual symposium on Parallelism in algorithms and architectures10.1145/1378533.1378573(197-206)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1378533.1378573
Golander AWeiss S(2008)Hiding the misprediction penalty of a resource-efficient high-performance processorACM Transactions on Architecture and Code Optimization10.1145/1328195.13282014:4(1-32)Online publication date: 30-Jan-2008
https://dl.acm.org/doi/10.1145/1328195.1328201
Gabor RWeiss SMendelson A(2007)Fairness enforcement in switch on event multithreadingACM Transactions on Architecture and Code Optimization10.1145/1275937.12759394:3(15-es)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1145/1275937.1275939
Ganusov IBurtscher M(2006)Future executionACM Transactions on Architecture and Code Optimization10.1145/1187976.11879793:4(424-449)Online publication date: 1-Dec-2006
https://dl.acm.org/doi/10.1145/1187976.1187979
Ganusov IBurtscher MAltman ESkadron KZorn B(2006)Efficient emulation of hardware prefetchers via event-driven helper threadingProceedings of the 15th international conference on Parallel architectures and compilation techniques10.1145/1152154.1152178(144-153)Online publication date: 16-Sep-2006
https://dl.acm.org/doi/10.1145/1152154.1152178
Hudson RSaha BAdl-Tabatabai AHertzberg BPetrank EMoss E(2006)McRT-MallocProceedings of the 5th international symposium on Memory management10.1145/1133956.1133967(74-83)Online publication date: 10-Jun-2006
https://dl.acm.org/doi/10.1145/1133956.1133967
Saha BAdl-Tabatabai AHudson RMinh CHertzberg BTorrellas JChatterjee S(2006)McRT-STMProceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming10.1145/1122971.1123001(187-197)Online publication date: 29-Mar-2006
https://dl.acm.org/doi/10.1145/1122971.1123001
Gabor RWeiss SMendelson A(2006)Fairness and Throughput in Switch on Event MultithreadingProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2006.25(149-160)Online publication date: 9-Dec-2006
https://dl.acm.org/doi/10.1109/MICRO.2006.25

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Recommendations

Evaluating multi-core and many-core architectures through accelerating the three-dimensional Lax-Wendroff correction stencil

Optimized HPL for AMD GPU and multi-core CPU usage

Boundary element quadrature schemes for multi- and many-core architectures

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