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Hierarchical Ensemble Reduction and Learning for Resource-constrained Computing

Published: 04 December 2019 Publication History

Abstract

Generic tree ensembles (such as Random Forest, RF) rely on a substantial amount of individual models to attain desirable performance. The cost of maintaining a large ensemble could become prohibitive in applications where computing resources are stringent. In this work, a hierarchical ensemble reduction and learning framework is proposed. Experiments show our method consistently outperforms RF in terms of both accuracy and retained ensemble size. In other words, ensemble reduction is achieved with enhancement in accuracy rather than degradation. The method can be executed efficiently, up to >590× time reduction than a recent ensemble reduction work. We also developed Boolean logic encoding techniques to directly tackle multiclass problems. Moreover, our framework bridges the gap between software-based ensemble methods and hardware computing in the IoT era. We developed a novel conversion paradigm that supports the automatic deployment of >500 trees on a chip. Our proposed method reduces power consumption and overall area utilization by >21.5% and >62%, respectively, comparing with RF. The hierarchical approach provides rich opportunities to balance between the computation (training and response time), the hardware resource (memory and energy), and accuracy.

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  • (2024)Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-ChipIEEE Access10.1109/ACCESS.2024.338271012(48750-48763)Online publication date: 2024
  • (2023)SWEP-RFJournal of King Saud University - Computer and Information Sciences10.1016/j.jksuci.2023.10167235:8Online publication date: 1-Sep-2023

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Published In

ACM Transactions on Design Automation of Electronic Systems  Volume 25, Issue 1
January 2020
299 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/3370083
  • Editor:
  • Naehyuck Chang
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 December 2019
Accepted: 01 September 2019
Revised: 01 August 2019
Received: 01 May 2019
Published in TODAES Volume 25, Issue 1

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Author Tags

  1. Boolean logic
  2. Ensemble reduction
  3. edge computing
  4. hardware and energy efficiency
  5. hardware implementation
  6. hierarchical learning
  7. logic minimization
  8. machine learning

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  • Research
  • Refereed

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  • National Natural Science Foundation of China (NSFC)

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Cited By

View all
  • (2024)Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-ChipIEEE Access10.1109/ACCESS.2024.338271012(48750-48763)Online publication date: 2024
  • (2023)SWEP-RFJournal of King Saud University - Computer and Information Sciences10.1016/j.jksuci.2023.10167235:8Online publication date: 1-Sep-2023

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