Abstract
An ultra-low power consumption two-stage mixed switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented. Using two simple switches, the novel switching scheme divides the capacitor arrays into two sub-arrays: stage-one and stage-two arrays. The two sub-arrays convert high and low bits cycles, respectively. Once the high bits conversion cycles are completed, the corresponding sub-arrays are split off from the capacitor arrays. This decreases the number of capacitors used in the rest conversion procedure. Thus, the proposed method improves the energy efficiency of SAR ADC. Thanks to C–2C dummy capacitors and two-stage capacitor arrays, the novel architecture achieves 86% reduction in capacitor area than conventional SAR ADC. Furthermore, based on the charge sharing technique and monotonic switching method, the proposed switching scheme does not consume reset energy and achieves 99.8% less switching energy than the conventional switching method. In addition, the proposed scheme is less sensitive to capacitor mismatch because of its great performance in linearity.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
S.-U. Baek, K.-Y. Lee, M. Lee, Energy-efficient switching scheme for SAR ADC using zero-energy dual capacitor switching. Analog Integr. Circuits Signal Process. 94, 317–322 (2018)
F. Chen, A.P. Chandrakasan, V. Stojanovic, A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs, in IEEE Custom Integrated Circuits Conference (CICC) (2010), pp. 1–4
Z. Ding, W. Bai, Z. Zhu, Trade-off between energy and linearity switching scheme for SAR ADC. Analog Integr. Circuits Signal Process. 86, 121–125 (2016)
B. Ghanavati, E. Abiri, M.R. Salehi, A. Keyhani, A. Sanyal, LSB split capacitor SAR ADC with 99.2% switching energy reduction. Analog Integr. Circuits Signal Process. 93, 375–382 (2017)
A.R. Ghasemi, M. Saberi, R. Lotfi, A low-power capacitor switching scheme with low common-mode voltage variation for successive approximation ADC. Microelectron. J. 61, 15–20 (2017)
W. Guo, Z. Zhu, A 0.3 V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors. Microelectron. J. 68, 44–54 (2017)
Y.F. Hu, Z.C. Yi, Z.H. He, B. Li, Energy-efficient, area-efficient, high-accuracy and low-complexity switching scheme for SAR ADC. IEICE Electron. Express 14, 1–7 (2017)
H. Liang, R. Ding, S. Liu, Z. Zhu, Energy-efficient and area-efficient asymmetric capacitor switching scheme for SAR ADCs. J. Circuits Systems and Computers 27, 1850109 (2017)
Y.H. Liang, Z. Zhu, An energy-efficient switching scheme for low-power SAR ADC design. J. Circuits Syst. Comput. 27, 1850015 (2018)
C.C. Liu, S.J. Chang, G.Y. Huang, Y.Z. Lin, A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J. Solid-State Circuits 45, 731–740 (2010)
J. Liu, R. Ding, S. Liu, Z. Zhu, A highly energy-efficient, highly area-efficient capacitance multiplexing switching scheme for SAR ADC. Analog Integr. Circuits Signal. Process. 96, 207–215 (2018)
S.A. Mahmoud, H.A. Salem, H.M. Albalooshi, An 8-bit, 10KS/s, 1.87 µW successive approximation analog to digital converter in 0.25 µm CMOS technology for ECG detection systems. Circuits Syst. Signal Process. 34, 2419–2439 (2015)
D. Osipov, S. Paul, Two-step reset method for energy-efficient SAR ADC switching schemes. Electron. Lett. 52, 816–817 (2016)
A. Sanyal, N. Sun, SAR ADC architecture with 98% reduction in switching energy over conventional scheme. Electron. Lett. 49, 248–250 (2013)
S. Sarafi, A.K.B. Aain, J. Abbaszadeh, High-linear, energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs. Microelectron. J. 45, 288–296 (2014)
X. Tong, M. Ghovanloo, Energy-efficient switching scheme in SAR ADC for biomedical electronics. Electron. Lett. 51, 676–678 (2015)
X. Tong, Y. Zhang, 98.8% switching energy reduction in SAR ADC for bioelectronics application. Electron. Lett. 51, 1052–1054 (2015)
X. Tong, Y. Chen, Low-power high-linearity switching procedure for charge-redistribution SAR ADC. Circuits Systems and Signal Processing 36, 3825–3834 (2017)
S. Ur Rehman, A.M. Kamboh, A CMOS micro-power and area efficient neural recording and stimulation front-end for biomedical applications. Circuits Syst. Signal Process. 34, 1725–1746 (2015)
H. Wang, C.Y. Liu, W.M. Xie, Q.D. Zhang, Tri-level capacitor-splitting switching scheme with high energy-efficiency for SAR ADCs. IEICE Electron. Express 13, 1–5 (2016)
H. Wang, W.M. Xie, Z.X. Chen, S.J. Cai, A capacitor-splitting switching scheme with low total power consumption for SAR ADCs. J. Circuits Syst. Comput. 28(04), 1920002 (2018)
A. Wu, J. Wu, Energy-efficient switching scheme for ultra-low voltage SAR ADC. Analog Integr. Circuits Signal Process. 90, 507–511 (2017)
Y. Wu, X. Cheng, X. Zeng, A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme. Microelectron. J. 44, 1260–1267 (2013)
L.B. Xie, G.J. Wen, J.X. Liu, Y. Wang, Energy-efficient hybrid capacitor switching scheme for SAR ADC. Electron. Lett. 50, 22–23 (2014)
L. Xie, W. Nie, X. Yang, M. Zhou, A group reset method for energy-efficient SAR ADC switching schemes. Analog Integr. Circuits Signal Process. 96, 183–187 (2018)
L. Xie, J. Su, Y. Wang, J. Liu, G. Wen, Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs. Analog Integr. Circuits Signal Process. 90, 681–686 (2017)
B. Yazdani, A. Khorami, M. Sharifkhani, Low-power DAC with charge redistribution sampling method for SAR ADCs. Electron. Lett. 52, 187–188 (2016)
T. Yousefi, A. Dabbaghian, M. Yavari, An energy-efficient DAC switching method for SAR ADCs. IEEE Trans. Circuits Syst. II Exp. Briefs 1, 41–45 (2018)
C. Yuan, Y. Lam, Low-energy and area-efficient tri-level switching scheme for SAR ADC. Electron. Lett. 48, 482–483 (2012)
Y. Zhang, Y. Li, Z. Zhu, A charge-sharing switching scheme for SAR ADCs in biomedical applications. Microelectron. J. 75, 128–136 (2018)
Y. Zhu, C.H. Chan, U.F. Chio, S.W. Sin, U. Seng-Pan, R.P. Martins, F. Maloberti, A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE J. Solid-State Circuits 45, 1111–1121 (2010)
Z. Zhu, Y. Xiao, X. Song, V CM-based monotonic capacitor switching scheme for SAR ADC. Electron. Lett. 49, 327–329 (2013)
H.Y. Zhuang, Z. Zhu, Y.T. Yang, A 19-nW 0.7-V CMOS voltage reference with no amplifiers and no clock circuits. IEEE Trans. Circuits Syst. II Exp. Briefs 11, 830–834 (2014)
H.Y. Zhuang, W.J. Guo, J.X. Liu, H. Tang, Z. Zhu, L. Chen, N. Sun, A second-order noise-shaping SAR ADC with passive integrator and tri-level voting.IEEE J. Solid-State Circuits 54, 1636–1647 (2019)
Acknowledgements
This work is supported by the National Natural Science Foundation of China (No. 61306033) and the Science and Technology on Low-Light-Level Night Vision Laboratory (No. 61424120503162412005).
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Chen, Y., Zhuang, Y. & Tang, H. A 99.8% Energy-Reduced Two-Stage Mixed Switching Scheme for SAR ADC Without Reset Energy. Circuits Syst Signal Process 38, 5426–5447 (2019). https://doi.org/10.1007/s00034-019-01151-9
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-019-01151-9