Idle power consumption is becoming an important parameter in portable embedded system design where excessive quiescent power dissipation can lead to excessive heat generation and reliability issues in nanometer-scale CMOS. To address some of these ...

In this paper, an analytical framework to model crosstalk in sub-threshold regime of buffer driven capacitively coupled interconnects has been carried out. The proposed analytical model captures waveform shape and noise peaks quite efficiently. It is ...

We propose an ultra-low power memory design method based on the ultra-low ( $$\sim $$ ~ 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during ...