Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions
Article No.: 28, Pages 1 - 25
Abstract
In this article, we investigate the application of different techniques for mitigating the impact of process variations on the custom functional unit (CFU) of extensible processors. The techniques include using extra cycles for the CFU and extending the clock period for the extensible processor. The former technique is based on providing an extra clock cycle to those custom instructions (CIs) that have timing yields smaller than one. For this purpose, we make use of a lookup table (LUT) for each fabricated processor. Based on a post-fabrication analysis, the need for an extra clock cycle for some CIs is determined. Consequently, the CI timing violations are prevented, and all manufactured extensible processors will work with a predefined clock cycle time. To study the effect of the objective function (used during the CI selection phase) on the efficacy of the suggested architectural technique, we investigate three different objective functions. In the second technique, the clock period extension is used to guarantee a design yield of one. Our results demonstrate that combining both techniques helps increase the speedup achieved by the extensible processor. To assess the efficacies of the proposed methods, several benchmarks from different application domains are used. Results of the study reveal that the suggested techniques provide considerable improvements in the speedups of the extensible processors when compared to those of approaches that do not consider the impact of process variations.
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Index Terms
- Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions
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January 2016
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Publication History
Published: 28 January 2016
Accepted: 01 September 2015
Revised: 01 April 2015
Received: 01 January 2015
Published in TODAES Volume 21, Issue 2
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