research-article

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator

Authors:

Guillem López-Paradís,

Adrià Armejach,

Miquel MoretóAuthors Info & Claims

ICPP '21: Proceedings of the 50th International Conference on Parallel Processing

Article No.: 29, Pages 1 - 11

https://doi.org/10.1145/3472456.3472461

Published: 05 October 2021 Publication History

Abstract

In recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system in which the design will operate. This hinders proper testing and debugging of functionalities, and does not allow co-designing the accelerator to obtain a balanced and efficient architecture.

In this paper, we introduce gem5 + rtl, a flexible framework that enables simulation of RTL models inside a full-system software simulator. We present the framework’s functionality that allows easy integration of RTL models on a simulated system-on-chip (SoC) that is able to boot Linux and run complex multi-threaded and multi-programmed workloads. We demonstrate the framework with two relevant use cases that integrate a multi-core SoC with a Performance Monitoring Unit (PMU) and the NVIDIA Deep Learning Accelerator (NVDLA), showcasing how the framework enables testing RTL model features and how it can enable co-design taking into account the entire SoC.

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Cited By

Lai CZhang W(2024)gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-ChipsACM Transactions on Design Automation of Electronic Systems10.1145/366199729:5(1-20)Online publication date: 29-Apr-2024
https://dl.acm.org/doi/10.1145/3661997
Tian FWang KHan J(2024)Backward-Edge Control Flow Integrity Based on Return Address Encryption2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)10.1109/ICSICT62049.2024.10831556(1-3)Online publication date: 22-Oct-2024
https://doi.org/10.1109/ICSICT62049.2024.10831556
Fu CWang ZHan J(2024)Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00027(133-139)Online publication date: 2-Sep-2024
https://doi.org/10.1109/FPL64840.2024.00027
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ICPP '21: Proceedings of the 50th International Conference on Parallel Processing

August 2021

927 pages

ISBN:9781450390682

DOI:10.1145/3472456

Copyright © 2021 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 October 2021

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Research-article
Research
Refereed limited

Funding Sources

ERDF Operational Program of Catalonia 2014-2020
Ministerio de Ciencia, Innovación y Universidades
Horizon 2020 Framework Programme
Juan de la Cierva postdoctoral fellowship
Ajuts per a la contractació de personal investigador novell
Ramón y Cajal fellowship

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ICPP 2021

ICPP 2021: 50th International Conference on Parallel Processing

August 9 - 12, 2021

IL, Lemont, USA

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Overall Acceptance Rate 91 of 313 submissions, 29%

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Cited By

Lai CZhang W(2024)gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-ChipsACM Transactions on Design Automation of Electronic Systems10.1145/366199729:5(1-20)Online publication date: 29-Apr-2024
https://dl.acm.org/doi/10.1145/3661997
Tian FWang KHan J(2024)Backward-Edge Control Flow Integrity Based on Return Address Encryption2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)10.1109/ICSICT62049.2024.10831556(1-3)Online publication date: 22-Oct-2024
https://doi.org/10.1109/ICSICT62049.2024.10831556
Fu CWang ZHan J(2024)Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification2024 34th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL64840.2024.00027(133-139)Online publication date: 2-Sep-2024
https://doi.org/10.1109/FPL64840.2024.00027
Mao FGuo YLiao XJin HZhang WLiu HZheng LLiu XJiang ZZheng X(2023)Accelerating Loop-Oriented RTL Simulation With Code InstrumentationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.327693942:12(4985-4998)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3276939
Nema SChunduru SKodigal CVoskuilen GRodrigues AHemmert SFeinberg BLee HAwad AHughes C(2023)ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit2023 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC59245.2023.00038(196-200)Online publication date: 1-Oct-2023
https://doi.org/10.1109/IISWC59245.2023.00038
Castells-Rufas DMartorell XRoca AKropotov ATeruel XCervero TDavis J(2023)Ethernet Emulation over PCIe for RISC-V Software Development Vehicles2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS58620.2023.10335994(1-6)Online publication date: 15-Nov-2023
https://doi.org/10.1109/DCIS58620.2023.10335994
Wang ZFu CHan J(2023)Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396658(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10396658
López-Paradís GVenu BArmejach AMoretó M(2023)Characterization of a Coherent Hardware Accelerator Framework for SoCsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-46077-7_7(91-106)Online publication date: 2-Jul-2023
https://dl.acm.org/doi/10.1007/978-3-031-46077-7_7
Marino AHalinge NFons FArostegui J(2022)Build Automation Framework for Design Validation of Automotive Gateway Controllers2022 IFIP Networking Conference (IFIP Networking)10.23919/IFIPNetworking55013.2022.9829801(1-6)Online publication date: 13-Jun-2022
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Silveira JCastro LAraujo VZeli RLazari DGuedes MAzevedo RWanner L(2022)Prof5: A RISC-V profiler tool2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD55451.2022.00031(201-210)Online publication date: Nov-2022
https://doi.org/10.1109/SBAC-PAD55451.2022.00031

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