计算机科学 ›› 2015, Vol. 42 ›› Issue (7): 114-117.doi: 10.11896/j.issn.1002-137X.2015.07.024
宋国治 张大坤 涂 遥 黄 翠 王莲莲
SONG Guo-zhi ZHANG Da-kun TU Yao HUANG Cui WANG Lian-lian
摘要: 提出了一种改进的基于粒子群算法的优化布局算法(Improved Particle Swarm Optimization,IPSO)来替换原有的基于模拟退火(Simulated Annealing,SA)算法的优化布局算法,使其更加适用于大型三维片上网络的仿真。通过比较这两种算法的基本思想,给出了这两种算法的实现步骤并详细介绍了IPSO算法的改进思路。最后利用一款现有的三维片上网络仿真器进行了仿真验证。结果表明,提出的IPSO算法比原来的SA算法更适用于大型三维片上网络的仿真。
[1] Wang Jia-wen.Research of Key Issues on Three DementionalNetwork on Chip[D].Nanjing:Nanjing University,2012 [2] Jeang Y L,Wey T H,Wang H Y,et al.Mesh-Tree Architecture for Network-on-chip Design[C]∥International Conference on Innovative Computing Information and Control(ICICIC).2007:1-4 [3] Kangmin L,Se-Joong L,Donghyun K,et al.Networks-on-chipand networks-in-package for high-performance SoC platforms[C]∥2005 IEEE Asian Solid-State Circuits Conference.2005:485-488 [4] Ouyang Jin,Xie Jing,Matthew P,et al.Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip[C]∥IEEE/ACM International Conference on Computer-Aided Design(ICCAD).2010:477-482 [5] Nandakumar Vivek S,Marek-Sadowska M.Low power,highthroughput network-on-chip fabric for 3D multicore processors[C]∥IEEE International Conference on Computer Design(ICCD).2011:453-454 [6] Murali S,De Micheli G,et al.Bandwidth-Constrained Mapping of Cores onto NoC Architectures[C]∥Proc.DATE’04.2004:896-901 [7] Lafi W,Lattard D,Jerraya A,et al.An efficient hierarchical router for large 3D NoCs[C]∥2010 21st IEEE International Symposium on Rapid System Prototyping(RSP).2010:1-5 [8] Somasundaram K,Viswanathan N,et al.Performance Analysis of Cluster based 3D Routing Algorithms for NoC[C]∥2011 IEEE Recent Advances in Intelligent Computational Systems(RAICS).2011:157-162 (下转第124页)(上接第117页) [9] Dong Shao-zhou.The Desigh and Research of Routing algorithm and Simulation Model on Network on Chips,master dissertation[D].Hefei:Hefei University of Technology,2009 [10] Chen Yi-ou.Research on the network on chip architecture of oriented real-time complex systems and the mapping of technology[D].Chengdu:University of Electronic Science and Technology of China,2012 [11] Ababei C,de Paulo V,et al.3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans[J].International Journal of Reconfigurable Computing,2010 [12] Wang Ding-wei,Wang Jun-wei,Wang Hong-feng.IntelligentOptimization Methods[M].Higher Education Press,2007 [13] Yu Gang.The improved PSO algorithm and its application[M].Chengdu:Chengdu University of Technology [14] Mineo C,Jenkal R,Melamed S,et al.Interdie signaling in three dimensional integrated circuits[C]∥Proceedings of IEEE Custom Integrated Circuits Conference (CICC ’08).2008:655-658 [15] Rabaey J M.Digital Integrated Circuits:A Design Perspective(2nd edition)[M].Upper Saddle River,NJ,USA:Prentice-Hall,2003 |
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