Published: April 01, 2014Manuscript Received: September 09, 2013Released on J-STAGE: April 01, 2014Accepted: -
Advance online publication: -
Manuscript Revised: November 21, 2013
This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189MHz, outperforms the software-based SSL protocol.
