basic_verilog

Some basic must-have verilog modules

(licensed under CC BY-SA 4_0)

Author: Konstantin Pavlov, pavlovconst@gmail.com

/Advanced Synthesis Cookbook/ - useful code from Altera's cookbook
/KCPSM6_Release9_30Sept14/ - Xilinx's Picoblaze soft processor
/pacoblaze-2.2/ - version of Picoblaze adapted for Altera devices
/scripts/ - useful TCL scripts
/scripts/allow_undefined_ports.tcl - allows generation of test projects with undefined pins for Vivado IDE
/scripts/compile_quartus.tcl - boilerplate script for commandline project compilation in Quartus IDE
/scripts/convert_sof_to_jam.bat - Altera/Intel FPGA configuration file converter
/scripts/convert_sof_to_rbf.bat - another Altera/Intel FPGA configuration file converter
/scripts/iverilog_compile.tcl - complete script to compile Verilog sources with iverilog tool and run simulation in gtkwave tool
/scripts/modelsim_compile.tcl - Modelsim no-project-mode compilation script
/scripts/post_flow_quartus.tcl - custom reporting or report analisys for Intel Quartus IDE
/scripts/post_flow_vivado.tcl - custom reporting or report analisys for Xilinx Vivado IDE
/scripts/program_all.bat - command line programmer example for Altera/Intel FPGAs
/scripts/project_version_auto_increment.tcl - project version autoincrement script for Quartus IDE
/scripts/quartus_system_console_init.tcl - initialization script for reading/writing Avalon-MM through JTAG-to-Avalon-MM bridge IP
/scripts/set_project_directory.tcl - changes current directory to match project directory in Vivado IDE
/scripts/write_avalon_mm_from_file.tcl - writing bulk binary data from binary file to Avalon-MM through JTAG-to-Avalon-MM bridge IP
main_tb.sv - basic testbench template
ActionBurst - multichannel one-shot triggering module
ActionBurst2 - multichannel one-shot triggering with variable steps
adder_tree - adding multiple values together in parallel
bin2gray - combinational Gray code to binary converter
bin2pos - converts binary coded value to positional (one-hot) code
clk_divider - wide reference clock divider
debounce - two-cycle debounce for input buttons
delay - VERY USEFUL MODULE to make static delays or to synchronize across clock domains
dynamic_delay - dynamic delay for arbitrary input signal
edge_detect - combinational edge detector, gives one-tick pulses on every signal edge
encoder - digital encoder input logic module
fifo - single-clock FIFO buffer (queue) implementation
gray2bin - combinational binary to Gray code converter
leave_one_hot - combinational module that leaves only lowest hot bit
lifo - single-clock LIFO buffer (stack) implementation
NDivide - primitive integer divider
pos2bin - converts positional (one-hot) value to binary representation
pos2bin - converts positional (one-hot) value to binary representation
prbs_gen_chk - PRBS pattern generator or checker
pulse_gen - generates pulses with given width and delay
pulse_stretch - configurable pulse stretcher/extender module
reset_set - SR trigger variant w/o metastable state, set dominates here
reverse_bytes - reverses bytes order within multi-byte array
reverse_vector - reverses signal order within multi-bit bus
set_reset - SR trigger variant w/o metastable state, reset dominates here
spi_master - universal spi master module
UartRx - straightforward yet simple UART receiver implementation for FPGA written in Verilog
UartTx - straightforward yet simple UART transmitter implementation for FPGA written in Verilog
UartRxExtreme - extreme minimal UART receiver implementation for FPGA written in Verilog
UartTxExtreme - extreme minimal UART transmitter implementation for FPGA written in Verilog

Also added testbenches for selected modules

Name		Name	Last commit message	Last commit date
Latest commit History 106 Commits
Advanced Synthesis Cookbook		Advanced Synthesis Cookbook
KCPSM6_Release9_30Sept14		KCPSM6_Release9_30Sept14
avalon_mm_master_templates		avalon_mm_master_templates
example_projects		example_projects
license		license
pacoblaze-2.2		pacoblaze-2.2
scripts		scripts
ActionBurst.v		ActionBurst.v
ActionBurst2.v		ActionBurst2.v
ActionBurst2_tb.v		ActionBurst2_tb.v
ActionBurst_tb.v		ActionBurst_tb.v
NDivide.v		NDivide.v
README.md		README.md
UartRx.v		UartRx.v
UartRxExtreme.v		UartRxExtreme.v
UartTx.v		UartTx.v
UartTxExtreme.v		UartTxExtreme.v
UartTxExtreme_UartRxExtreme_tb.v		UartTxExtreme_UartRxExtreme_tb.v
UartTx_UartRx_tb.v		UartTx_UartRx_tb.v
adder_tree.sv		adder_tree.sv
adder_tree_tb.sv		adder_tree_tb.sv
bin2gray.sv		bin2gray.sv
bin2pos.sv		bin2pos.sv
bin2pos_tb.sv		bin2pos_tb.sv
clk_divider.sv		clk_divider.sv
debounce.v		debounce.v
debounce_tb.v		debounce_tb.v
delay.sv		delay.sv
delay_tb.sv		delay_tb.sv
dynamic_delay.sv		dynamic_delay.sv
dynamic_delay_tb.sv		dynamic_delay_tb.sv
edge_detect.sv		edge_detect.sv
edge_detect_tb.sv		edge_detect_tb.sv
encoder.v		encoder.v
encoder_tb.v		encoder_tb.v
fifo.sv		fifo.sv
fifo_tb.sv		fifo_tb.sv
gray2bin.sv		gray2bin.sv
gray_tb.sv		gray_tb.sv
leave_one_hot.sv		leave_one_hot.sv
leave_one_hot_tb.sv		leave_one_hot_tb.sv
lifo.sv		lifo.sv
lifo_tb.sv		lifo_tb.sv
main_tb.sv		main_tb.sv
pack_unpack_array.v		pack_unpack_array.v
pdm_modulator.sv		pdm_modulator.sv
pdm_modulator_tb.png		pdm_modulator_tb.png
pdm_modulator_tb.sv		pdm_modulator_tb.sv
pos2bin.sv		pos2bin.sv
pos2bin_tb.sv		pos2bin_tb.sv
prbs_gen_chk.sv		prbs_gen_chk.sv
prbs_gen_chk_tb.sv		prbs_gen_chk_tb.sv
preview_fifo.sv		preview_fifo.sv
preview_fifo_tb.sv		preview_fifo_tb.sv
pulse_gen.sv		pulse_gen.sv
pulse_gen_tb.sv		pulse_gen_tb.sv
pulse_stretch.sv		pulse_stretch.sv
pulse_stretch_tb.sv		pulse_stretch_tb.sv
pwm_modulator.sv		pwm_modulator.sv
pwm_modulator_tb.png		pwm_modulator_tb.png
pwm_modulator_tb.sv		pwm_modulator_tb.sv
reset_set.sv		reset_set.sv
reset_set_comb.sv		reset_set_comb.sv
reverse_bytes.sv		reverse_bytes.sv
reverse_dimensions.sv		reverse_dimensions.sv
reverse_dimensions_tb.sv		reverse_dimensions_tb.sv
reverse_vector.sv		reverse_vector.sv
reverse_vector_tb.sv		reverse_vector_tb.sv
set_reset.sv		set_reset.sv
set_reset_comb.sv		set_reset_comb.sv
spi_master.sv		spi_master.sv
spi_master_tb.sv		spi_master_tb.sv
vm80a.v		vm80a.v

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