If pendSV is serviced during an LDM/STM instruction, which is interruptible and uses XPSR "ICI/IT" bitfield to save load/store progress, it may causes INVSTATE type hardfault when CPU finally returns to nlr_jump().
This is because on exception return, the Cortex-M core is expecting to resume LDM/STM when it sees the valid progress information in unstacked ICI/IT field of XPSR register
However, pendSV returns to nlr_jump(). So there is no LDM/STM instruction and the Cortex-M CPU generates hardfault with INVSTATE.
My workaround, insert below instructions in the beginning of PendSV_Handler:
"mov r2, #0x01000000 \n"
"str r2, [sp, #28] \n" // modify stacked XPSR to make sure possible LDM/STM progress is cleared

So when nlr_jump() is entered, it always has XPSR unstacked to a "clean" state.

Note: This may have something to do with the INVSTATE hardfault found in openMV project.