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drivers/memory/spiflash.c: Write 2nd byte of SR as separate command. #11932

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drivers/memory/spiflash.c: Write 2nd byte of SR as separate command. #11932

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62760e0
stm32/qspi.c: Allow qspi_write_cmd_data to write cmd with 1 data byte.
victorallume Jul 4, 2023
5d72f68
drivers/memory/spiflash.c: Write 2nd byte of SR as separate command.
victorallume Jul 4, 2023
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8 changes: 8 additions & 0 deletions drivers/memory/spiflash.c
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@
#define CMD_RDSR (0x05)
#define CMD_WREN (0x06)
#define CMD_SEC_ERASE (0x20)
#define CMD_WRCR (0x31) // sometimes referred to as SR byte 2
#define CMD_RDCR (0x35)
#define CMD_RD_DEVID (0x9f)
#define CMD_CHIP_ERASE (0xc7)
Expand Down Expand Up @@ -199,10 +200,17 @@ void mp_spiflash_init(mp_spiflash_t *self) {
}
uint32_t data = (sr & 0xff) | (cr & 0xff) << 8;
if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) {
// Write both bytes of SR
data |= QSPI_QE_MASK << 8;
mp_spiflash_write_cmd(self, CMD_WREN);
mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
mp_spiflash_wait_wip0(self);

// Write just byte 2 of SR for flash that only supports that mode of setting SR
data = (cr & 0xff) | QSPI_QE_MASK;
mp_spiflash_write_cmd(self, CMD_WREN);
mp_spiflash_write_cmd_data(self, CMD_WRCR, 1, data);
mp_spiflash_wait_wip0(self);
}
}

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8 changes: 6 additions & 2 deletions ports/stm32/qspi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -232,8 +232,12 @@ STATIC int qspi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t
while (!(QUADSPI->SR & QUADSPI_SR_FTF)) {
}

// This assumes len==2
*(uint16_t *)&QUADSPI->DR = data;
if (len == 1) {
*(uint8_t *)&QUADSPI->DR = data;
} else {
// This assumes len==2
*(uint16_t *)&QUADSPI->DR = data;
}
}

// Wait for write to finish
Expand Down
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