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-173
lines changed

7 files changed

+197
-173
lines changed

‎devices/fields/dbg/dbg_l0.yaml

Lines changed: 33 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,35 @@
11
# Debug registers for L0
22

3-
DBG:
4-
CR:
5-
DBG_STANDBY:
6-
Disabled: [0, Debug Standby Mode Disabled]
7-
Enabled: [1, Debug Standby Mode Enabled]
8-
DBG_STOP:
9-
Disabled: [0, Debug Stop Mode Disabled]
10-
Enabled: [1, Debug Stop Mode Enabled]
11-
DBG_SLEEP:
12-
Disabled: [0, Debug Sleep Mode Disabled]
13-
Enabled: [1, Debug Sleep Mode Enabled]
14-
APB1_FZ:
15-
DBG_LPTIMER_STOP:
16-
Continue: [0, LPTIM1 counter clock is fed even if the core is halted]
17-
Stop: [1, LPTIM1 counter clock is stopped when the core is halted]
18-
DBG_I2C*_STOP:
19-
NormalMode: [0, Same behavior as in normal mode]
20-
SMBusTimeoutFrozen: [1, I2C3 SMBUS timeout is frozen]
21-
DBG_IWDG_STOP:
22-
Continue: [0, The independent watchdog counter clock continues even if the core is halted]
23-
Stop: [1, The independent watchdog counter clock is stopped when the core is halted]
24-
DBG_WWDG_STOP:
25-
Continue: [0, The window watchdog counter clock continues even if the core is halted]
26-
Stop: [1, The window watchdog counter clock is stopped when the core is halted]
27-
DBG_RTC_STOP:
28-
Continue: [0, The clock of the RTC counter is fed even if the core is halted]
29-
Stop: [1, The clock of the RTC counter is stopped when the core is halted]
30-
DBG_TIM*_STOP:
31-
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
32-
Stop: [1, The counter clock of TIMx is stopped when the core is halted]
33-
APB2_FZ:
34-
DBG_TIM*_STOP:
35-
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
36-
Stop: [1, The counter clock of TIMx is stopped when the core is halted]
3+
CR:
4+
DBG_STANDBY:
5+
Disabled: [0, Debug Standby Mode Disabled]
6+
Enabled: [1, Debug Standby Mode Enabled]
7+
DBG_STOP:
8+
Disabled: [0, Debug Stop Mode Disabled]
9+
Enabled: [1, Debug Stop Mode Enabled]
10+
DBG_SLEEP:
11+
Disabled: [0, Debug Sleep Mode Disabled]
12+
Enabled: [1, Debug Sleep Mode Enabled]
13+
APB1_FZ:
14+
DBG_LPTIMER_STOP:
15+
Continue: [0, LPTIM1 counter clock is fed even if the core is halted]
16+
Stop: [1, LPTIM1 counter clock is stopped when the core is halted]
17+
DBG_I2C*_STOP:
18+
NormalMode: [0, Same behavior as in normal mode]
19+
SMBusTimeoutFrozen: [1, I2C3 SMBUS timeout is frozen]
20+
DBG_IWDG_STOP:
21+
Continue: [0, The independent watchdog counter clock continues even if the core is halted]
22+
Stop: [1, The independent watchdog counter clock is stopped when the core is halted]
23+
DBG_WWDG_STOP:
24+
Continue: [0, The window watchdog counter clock continues even if the core is halted]
25+
Stop: [1, The window watchdog counter clock is stopped when the core is halted]
26+
DBG_RTC_STOP:
27+
Continue: [0, The clock of the RTC counter is fed even if the core is halted]
28+
Stop: [1, The clock of the RTC counter is stopped when the core is halted]
29+
DBG_TIM*_STOP:
30+
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
31+
Stop: [1, The counter clock of TIMx is stopped when the core is halted]
32+
APB2_FZ:
33+
DBG_TIM*_STOP:
34+
Continue: [0, The counter clock of TIMx is fed even if the core is halted]
35+
Stop: [1, The counter clock of TIMx is stopped when the core is halted]

‎devices/fields/pwr/pwr_l0.yaml

Lines changed: 102 additions & 103 deletions
Original file line numberDiff line numberDiff line change
@@ -1,109 +1,108 @@
11
# Power Controller for L0 Family
22

3-
PWR:
4-
_include:
5-
- pwr_v1.yaml
3+
_include:
4+
- pwr_v1.yaml
65

7-
CR:
8-
LPRUN:
9-
MAIN_MODE: [0, Voltage regulator in Main mode in Low-power run mode]
10-
LOW_POWER_MODE: [1, Voltage regulator in low-power mode in Low-power run mode]
11-
DS_EE_KOFF:
12-
NVMWakeUp: [0, NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set]
13-
NVMSleep: [1, NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)]
14-
VOS:
15-
V1_8: [1, 1.8 V (range 1)]
16-
V1_5: [2, 1.5 V (range 2)]
17-
V1_2: [3, 1.2 V (range 3)]
18-
FWU:
19-
Disabled: [0, Low-power modes exit occurs only when VREFINT is ready]
20-
Enabled: [1, VREFINT start up time is ignored when exiting low-power modes]
21-
ULP:
22-
Enabled: [0, VREFINT is on in low-power mode]
23-
Disabled: [1, VREFINT is off in low-power mode]
24-
DBP:
25-
Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"]
26-
Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"]
27-
"?~PLS":
28-
V1_9: [0, 1.9 V]
29-
V2_1: [1, 2.1 V]
30-
V2_3: [2, 2.3 V]
31-
V2_5: [3, 2.5 V]
32-
V2_7: [4, 2.7 V]
33-
V2_9: [5, 2.9 V]
34-
V3_1: [6, 3.1 V]
35-
External: [7, External input analog voltage (Compare internally to VREFINT)]
36-
"?~PVDE":
37-
Disabled: [0, PVD Disabled]
38-
Enabled: [1, PVD Enabled]
39-
CSBF:
40-
_write:
41-
Clear: [1, Clear the SBF Standby flag]
42-
CWUF:
43-
_write:
44-
Clear: [1, Clear the WUF Wakeup flag after 2 system clock cycles]
45-
LPSDSR:
46-
MAIN_MODE: [0, Voltage regulator on during Deepsleep/Sleep/Low-power run mode]
47-
LOW_POWER_MODE: [1, Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode]
48-
CSR:
49-
EWUP3:
50-
Disabled:
51-
[
52-
0,
53-
WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode,
54-
]
55-
Enabled:
56-
[
57-
1,
58-
WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode),
59-
]
60-
EWUP2:
61-
Disabled:
62-
[
63-
0,
64-
WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode,
65-
]
66-
Enabled:
67-
[
68-
1,
69-
WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode),
70-
]
71-
EWUP1:
72-
Disabled:
73-
[
74-
0,
75-
WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode,
76-
]
77-
Enabled:
6+
CR:
7+
LPRUN:
8+
MAIN_MODE: [0, Voltage regulator in Main mode in Low-power run mode]
9+
LOW_POWER_MODE: [1, Voltage regulator in low-power mode in Low-power run mode]
10+
DS_EE_KOFF:
11+
NVMWakeUp: [0, NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set]
12+
NVMSleep: [1, NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)]
13+
VOS:
14+
V1_8: [1, 1.8 V (range 1)]
15+
V1_5: [2, 1.5 V (range 2)]
16+
V1_2: [3, 1.2 V (range 3)]
17+
FWU:
18+
Disabled: [0, Low-power modes exit occurs only when VREFINT is ready]
19+
Enabled: [1, VREFINT start up time is ignored when exiting low-power modes]
20+
ULP:
21+
Enabled: [0, VREFINT is on in low-power mode]
22+
Disabled: [1, VREFINT is off in low-power mode]
23+
DBP:
24+
Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"]
25+
Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"]
26+
"?~PLS":
27+
V1_9: [0, 1.9 V]
28+
V2_1: [1, 2.1 V]
29+
V2_3: [2, 2.3 V]
30+
V2_5: [3, 2.5 V]
31+
V2_7: [4, 2.7 V]
32+
V2_9: [5, 2.9 V]
33+
V3_1: [6, 3.1 V]
34+
External: [7, External input analog voltage (Compare internally to VREFINT)]
35+
"?~PVDE":
36+
Disabled: [0, PVD Disabled]
37+
Enabled: [1, PVD Enabled]
38+
CSBF:
39+
_write:
40+
Clear: [1, Clear the SBF Standby flag]
41+
CWUF:
42+
_write:
43+
Clear: [1, Clear the WUF Wakeup flag after 2 system clock cycles]
44+
LPSDSR:
45+
MAIN_MODE: [0, Voltage regulator on during Deepsleep/Sleep/Low-power run mode]
46+
LOW_POWER_MODE: [1, Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode]
47+
CSR:
48+
EWUP3:
49+
Disabled:
50+
[
51+
0,
52+
WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode,
53+
]
54+
Enabled:
55+
[
56+
1,
57+
WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode),
58+
]
59+
EWUP2:
60+
Disabled:
61+
[
62+
0,
63+
WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode,
64+
]
65+
Enabled:
66+
[
67+
1,
68+
WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode),
69+
]
70+
EWUP1:
71+
Disabled:
72+
[
73+
0,
74+
WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode,
75+
]
76+
Enabled:
77+
[
78+
1,
79+
WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode),
80+
]
81+
REGLPF:
82+
_read:
83+
Ready: [0, Regulator is ready in Main mode]
84+
NotReady: [1, Regulator voltage is in low-power mode]
85+
VOSF:
86+
_read:
87+
Ready: [0, Regulator is ready in the selected voltage range]
88+
NotReady: [1, Regulator voltage output is changing to the required VOS level]
89+
VREFINTRDYF:
90+
_read:
91+
NotReady: [0, VREFINT is OFF]
92+
Ready: [1, VREFINT is ready]
93+
"?~PVDO":
94+
_read:
95+
AboveThreshold: [0, "VDD is higher than the PVD threshold selected with the PLS[2:0] bits"]
96+
BelowThreshold: [1, "VDD is lower than the PVD threshold selected with the PLS[2:0] bits"]
97+
SBF:
98+
_read:
99+
NoStandbyEvent: [0, Device has not been in Standby mode]
100+
StandbyEvent: [1, Device has been in Standby mode]
101+
WUF:
102+
_read:
103+
NoWakeupEvent: [0, No wakeup event occurred]
104+
WakeupEvent:
78105
[
79106
1,
80-
WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode),
107+
"A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)",
81108
]
82-
REGLPF:
83-
_read:
84-
Ready: [0, Regulator is ready in Main mode]
85-
NotReady: [1, Regulator voltage is in low-power mode]
86-
VOSF:
87-
_read:
88-
Ready: [0, Regulator is ready in the selected voltage range]
89-
NotReady: [1, Regulator voltage output is changing to the required VOS level]
90-
VREFINTRDYF:
91-
_read:
92-
NotReady: [0, VREFINT is OFF]
93-
Ready: [1, VREFINT is ready]
94-
"?~PVDO":
95-
_read:
96-
AboveThreshold: [0, "VDD is higher than the PVD threshold selected with the PLS[2:0] bits"]
97-
BelowThreshold: [1, "VDD is lower than the PVD threshold selected with the PLS[2:0] bits"]
98-
SBF:
99-
_read:
100-
NoStandbyEvent: [0, Device has not been in Standby mode]
101-
StandbyEvent: [1, Device has been in Standby mode]
102-
WUF:
103-
_read:
104-
NoWakeupEvent: [0, No wakeup event occurred]
105-
WakeupEvent:
106-
[
107-
1,
108-
"A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)",
109-
]

‎devices/patches/firewall/l0.yaml

Lines changed: 0 additions & 8 deletions
This file was deleted.

‎devices/stm32l0x0.yaml

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@ _delete:
88
_modify:
99
Flash:
1010
name: FLASH
11+
Firewall:
12+
name: FW
1113

1214
ADC:
1315
_include:
@@ -30,7 +32,11 @@ CRC:
3032
- fields/crc/crc_idr_8bit.yaml
3133
- fields/crc/crc_pol.yaml
3234

33-
DMA?:
35+
DBG:
36+
_include:
37+
- fields/dbg/dbg_l0.yaml
38+
39+
DMA1:
3440
_include:
3541
- fields/dma/dma_v1_with_remapping.yaml
3642
- collect/dma/v1.yaml
@@ -44,10 +50,11 @@ FLASH:
4450
- fields/flash/flash_l0.yaml
4551

4652
FW:
53+
_strip: FIREWALL_
4754
_include:
4855
- fields/fw/fw_l0_l4.yaml
4956

50-
GPIO?:
57+
GPIO[AB]:
5158
_include:
5259
- fields/gpio/gpio_g0_l0.yaml
5360
- collect/gpio/v2r.yaml
@@ -57,7 +64,7 @@ GPIO[A]:
5764
GPIO[B]:
5865
_include: collect/gpio/v2r_derive.yaml
5966

60-
I2C?:
67+
I2C1:
6168
_include:
6269
- fields/i2c/v2.yaml
6370

@@ -79,6 +86,8 @@ LPUART1:
7986
- fields/usart/v3/lp_A.yaml
8087

8188
PWR:
89+
_include:
90+
- fields/pwr/pwr_l0.yaml
8291
CR:
8392
# LPDS only exists in the L0x0 family
8493
LPDS:
@@ -126,7 +135,7 @@ RTC:
126135
- collect/rtc/alarm.yaml
127136
- collect/rtc/bkpr.yaml
128137

129-
SPI?:
138+
SPI1:
130139
_include:
131140
- patches/16bit.yaml
132141
- patches/spi/dr8.yaml
@@ -182,9 +191,6 @@ WWDG:
182191
- fields/wwdg/wwdg.yaml
183192

184193
_include:
185-
- patches/firewall/l0.yaml
186194
- patches/nvic/l0_prio_bits.yaml
187-
- fields/dbg/dbg_l0.yaml
188195
- fields/nvic/nvic_v1.yaml
189-
- fields/pwr/pwr_l0.yaml
190196
- patches/tim/group.yaml

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