stm32-rs · burrbull · Feb 7, 2025 · Feb 5, 2025 · Feb 5, 2025 · Feb 6, 2025
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -5,6 +5,7 @@
 * USART: refactor and add missing enums
 * STM32H503: Add missing RNG_NSCR register
 * Refactor timers, add enums
+* Add placeholders for all peripherals
 * STM32H5xx: Add H533 (#1129)
 * G4: Fix swapped reset values for SPI4 CR1 and CR2 by deriving SPI4 from SPI1 (#957)
 * STM32H5xx: Update SVD to version 1.7 and add H523 (#1124)

diff --git a/devices/collect/gtzc/h5_u5.yaml b/devices/collect/gtzc/h5_u5.yaml
@@ -8,6 +8,6 @@ _array:
     _array:
       PRIV*: {}
 
-CFGLOCK?,CFGLOCKR?:
+CFGLOCK,CFGLOCK?,CFGLOCKR?:
   _array:
     SPLCK*: {}
diff --git a/devices/fields/crs/crs.yaml b/devices/fields/crs/crs.yaml
@@ -1,53 +1,52 @@
-CRS:
-  CR:
-    TRIM: [0, 0x3F]
-    SWSYNC:
-      Sync: [1, A software sync is generated]
-    AUTOTRIMEN:
-      Disabled: [0, Automatic trimming disabled]
-      Enabled: [1, Automatic trimming enabled]
-    CEN:
-      Disabled: [0, Frequency error counter disabled]
-      Enabled: [1, Frequency error counter enabled]
-    "*IE":
-      Disabled: [0, Interrupt disabled]
-      Enabled: [1, Interrupt enabled]
+CR:
+  TRIM: [0, 0x3F]
+  SWSYNC:
+    Sync: [1, A software sync is generated]
+  AUTOTRIMEN:
+    Disabled: [0, Automatic trimming disabled]
+    Enabled: [1, Automatic trimming enabled]
+  CEN:
+    Disabled: [0, Frequency error counter disabled]
+    Enabled: [1, Frequency error counter enabled]
+  "*IE":
+    Disabled: [0, Interrupt disabled]
+    Enabled: [1, Interrupt enabled]
 
-  CFGR:
-    SYNCPOL:
-      RisingEdge: [0, SYNC active on rising edge]
-      FallingEdge: [1, SYNC active on falling edge]
-    SYNCSRC:
-      GPIO_AF: [0, GPIO AF (crs_sync_in_1) selected as SYNC signal source]
-      LSE: [1, LSE (crs_sync_in_2) selected as SYNC signal source]
-      USB_SOF: [2, USB SOF (crs_sync_in_3) selected as SYNC signal source]
-    SYNCDIV:
-      NotDivided: [0, SYNC not divided]
-      DivideBy2: [1, SYNC divided by 2]
-      DivideBy4: [2, SYNC divided by 4]
-      DivideBy8: [3, SYNC divided by 8]
-      DivideBy16: [4, SYNC divided by 16]
-      DivideBy32: [5, SYNC divided by 32]
-      DivideBy64: [6, SYNC divided by 64]
-      DivideBy128: [7, SYNC divided by 128]
-    FELIM: [0, 0xFF]
-    RELOAD: [0, 0xFFFF]
+CFGR:
+  SYNCPOL:
+    RisingEdge: [0, SYNC active on rising edge]
+    FallingEdge: [1, SYNC active on falling edge]
+  SYNCSRC:
+    GPIO_AF: [0, GPIO AF (crs_sync_in_1) selected as SYNC signal source]
+    LSE: [1, LSE (crs_sync_in_2) selected as SYNC signal source]
+    USB_SOF: [2, USB SOF (crs_sync_in_3) selected as SYNC signal source]
+  SYNCDIV:
+    NotDivided: [0, SYNC not divided]
+    DivideBy2: [1, SYNC divided by 2]
+    DivideBy4: [2, SYNC divided by 4]
+    DivideBy8: [3, SYNC divided by 8]
+    DivideBy16: [4, SYNC divided by 16]
+    DivideBy32: [5, SYNC divided by 32]
+    DivideBy64: [6, SYNC divided by 64]
+    DivideBy128: [7, SYNC divided by 128]
+  FELIM: [0, 0xFF]
+  RELOAD: [0, 0xFFFF]
 
-  ISR:
-    FECAP: [0, 0xFFFF]
-    FEDIR:
-      UpCounting: [0, Error in up-counting direction]
-      DownCounting: [1, Error in down-counting direction]
-    SYNCMISS:
-      NotSignaled: [0, Signal not set]
-      Signaled: [1, Signal set]
-    SYNCERR:
-      NotSignaled: [0, Signal not set]
-      Signaled: [1, Signal set]
-    "*F":
-      NotSignaled: [0, Signal not set]
-      Signaled: [1, Signal set]
+ISR:
+  FECAP: [0, 0xFFFF]
+  FEDIR:
+    UpCounting: [0, Error in up-counting direction]
+    DownCounting: [1, Error in down-counting direction]
+  SYNCMISS:
+    NotSignaled: [0, Signal not set]
+    Signaled: [1, Signal set]
+  SYNCERR:
+    NotSignaled: [0, Signal not set]
+    Signaled: [1, Signal set]
+  "*F":
+    NotSignaled: [0, Signal not set]
+    Signaled: [1, Signal set]
 
-  ICR:
-    "*C":
-      Clear: [1, Clear flag]
+ICR:
+  "*C":
+    Clear: [1, Clear flag]
diff --git a/devices/fields/dbg/dbg_l0.yaml b/devices/fields/dbg/dbg_l0.yaml
@@ -1,36 +1,35 @@
 # Debug registers for L0
 
-DBG:
-  CR:
-    DBG_STANDBY:
-      Disabled: [0, Debug Standby Mode Disabled]
-      Enabled: [1, Debug Standby Mode Enabled]
-    DBG_STOP:
-      Disabled: [0, Debug Stop Mode Disabled]
-      Enabled: [1, Debug Stop Mode Enabled]
-    DBG_SLEEP:
-      Disabled: [0, Debug Sleep Mode Disabled]
-      Enabled: [1, Debug Sleep Mode Enabled]
-  APB1_FZ:
-    DBG_LPTIMER_STOP:
-      Continue: [0, LPTIM1 counter clock is fed even if the core is halted]
-      Stop: [1, LPTIM1 counter clock is stopped when the core is halted]
-    DBG_I2C*_STOP:
-      NormalMode: [0, Same behavior as in normal mode]
-      SMBusTimeoutFrozen: [1, I2C3 SMBUS timeout is frozen]
-    DBG_IWDG_STOP:
-      Continue: [0, The independent watchdog counter clock continues even if the core is halted]
-      Stop: [1, The independent watchdog counter clock is stopped when the core is halted]
-    DBG_WWDG_STOP:
-      Continue: [0, The window watchdog counter clock continues even if the core is halted]
-      Stop: [1, The window watchdog counter clock is stopped when the core is halted]
-    DBG_RTC_STOP:
-      Continue: [0, The clock of the RTC counter is fed even if the core is halted]
-      Stop: [1, The clock of the RTC counter is stopped when the core is halted]
-    DBG_TIM*_STOP:
-      Continue: [0, The counter clock of TIMx is fed even if the core is halted]
-      Stop: [1, The counter clock of TIMx is stopped when the core is halted]
-  APB2_FZ:
-    DBG_TIM*_STOP:
-      Continue: [0, The counter clock of TIMx is fed even if the core is halted]
-      Stop: [1, The counter clock of TIMx is stopped when the core is halted]
+CR:
+  DBG_STANDBY:
+    Disabled: [0, Debug Standby Mode Disabled]
+    Enabled: [1, Debug Standby Mode Enabled]
+  DBG_STOP:
+    Disabled: [0, Debug Stop Mode Disabled]
+    Enabled: [1, Debug Stop Mode Enabled]
+  DBG_SLEEP:
+    Disabled: [0, Debug Sleep Mode Disabled]
+    Enabled: [1, Debug Sleep Mode Enabled]
+APB1_FZ:
+  DBG_LPTIMER_STOP:
+    Continue: [0, LPTIM1 counter clock is fed even if the core is halted]
+    Stop: [1, LPTIM1 counter clock is stopped when the core is halted]
+  DBG_I2C*_STOP:
+    NormalMode: [0, Same behavior as in normal mode]
+    SMBusTimeoutFrozen: [1, I2C3 SMBUS timeout is frozen]
+  DBG_IWDG_STOP:
+    Continue: [0, The independent watchdog counter clock continues even if the core is halted]
+    Stop: [1, The independent watchdog counter clock is stopped when the core is halted]
+  DBG_WWDG_STOP:
+    Continue: [0, The window watchdog counter clock continues even if the core is halted]
+    Stop: [1, The window watchdog counter clock is stopped when the core is halted]
+  DBG_RTC_STOP:
+    Continue: [0, The clock of the RTC counter is fed even if the core is halted]
+    Stop: [1, The clock of the RTC counter is stopped when the core is halted]
+  DBG_TIM*_STOP:
+    Continue: [0, The counter clock of TIMx is fed even if the core is halted]
+    Stop: [1, The counter clock of TIMx is stopped when the core is halted]
+APB2_FZ:
+  DBG_TIM*_STOP:
+    Continue: [0, The counter clock of TIMx is fed even if the core is halted]
+    Stop: [1, The counter clock of TIMx is stopped when the core is halted]