stm32-rs · burrbull · Feb 9, 2025 · Feb 8, 2025
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -7,6 +7,7 @@
 * Refactor timers, add enums
 * Add placeholders for all peripherals
 * STM32H5xx: Add H533 (#1129)
+* Fix DMA & collect
 * G4: Fix swapped reset values for SPI4 CR1 and CR2 by deriving SPI4 from SPI1 (#957)
 * STM32H5xx: Update SVD to version 1.7 and add H523 (#1124)
 * TIM3's CCRx is 16-bit for G0Bx and G0C0

diff --git a/devices/collect/dma/dmamux.yaml b/devices/collect/dma/dmamux.yaml
@@ -4,3 +4,20 @@ _array:
     description: DMA Multiplexer Channel %s Control register
   RG*CR:
     name: RGCR%s
+
+CSR:
+  _array:
+    SOF*:
+      description: Synchronization Overrun Flag %s
+"CFR,CCFR":
+  _array:
+    CSOF*:
+      description: Synchronization Clear Overrun Flag %s
+RGSR:
+  _array:
+    OF?:
+      description: Generator Overrun Flag %s
+RGCFR:
+  _array:
+    COF?:
+      description: Generator Clear Overrun Flag %s
diff --git a/devices/collect/dma/l5.yaml b/devices/collect/dma/l5.yaml
@@ -11,3 +11,6 @@ _cluster:
       name: M0AR
     CM1AR?:
       name: M1AR
+
+_include:
+  - isr_array.yaml
diff --git a/devices/fields/adc/adc_v3_f3.yaml b/devices/fields/adc/adc_v3_f3.yaml
@@ -1,7 +1,6 @@
 # ADC v3 with F3 specific fields
 
 _include:
-  - ../../patches/adc/split.yaml
   - adc_v3.yaml
 CR:
   ADVREGEN:

diff --git a/devices/fields/dma/common.yaml b/devices/fields/dma/common.yaml
@@ -0,0 +1,57 @@
+ISR:
+  TEIF*:
+    NoError: [0, No transfer error]
+    Error: [1, A transfer error has occured]
+  HTIF*:
+    NotHalf: [0, No half transfer event]
+    Half: [1, A half transfer event has occured]
+  TCIF*:
+    NotComplete: [0, No transfer complete event]
+    Complete: [1, A transfer complete event has occured]
+  GIF*:
+    NoEvent: [0, "No transfer error, half event, complete event"]
+    Event: [1, "A transfer error, half event or complete event has occured"]
+IFCR:
+  CTEIF*:
+    Clear: [1, Clears the TEIF flag in the ISR register]
+  CHTIF*:
+    Clear: [1, Clears the HTIF flag in the ISR register]
+  CTCIF*:
+    Clear: [1, Clears the TCIF flag in the ISR register]
+  CGIF*:
+    Clear: [1, "Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register"]
+
+CCR*:
+  MEM2MEM:
+    Disabled: [0, Memory to memory mode disabled]
+    Enabled: [1, Memory to memory mode enabled]
+  PL:
+    Low: [0, Low priority]
+    Medium: [1, Medium priority]
+    High: [2, High priority]
+    VeryHigh: [3, Very high priority]
+  "[MP]SIZE":
+    Bits8: [0, 8-bit size] # or Byte
+    Bits16: [1, 16-bit size] # or HalfWord
+    Bits32: [2, 32-bit size] # or Word
+  "[MP]INC":
+    Disabled: [0, Increment mode disabled]
+    Enabled: [1, Increment mode enabled]
+  CIRC:
+    Disabled: [0, Circular buffer disabled]
+    Enabled: [1, Circular buffer enabled]
+  DIR:
+    FromPeripheral: [0, Read from peripheral]
+    FromMemory: [1, Read from memory]
+  TEIE:
+    Disabled: [0, Transfer Error interrupt disabled]
+    Enabled: [1, Transfer Error interrupt enabled]
+  HTIE:
+    Disabled: [0, Half Transfer interrupt disabled]
+    Enabled: [1, Half Transfer interrupt enabled]
+  TCIE:
+    Disabled: [0, Transfer Complete interrupt disabled]
+    Enabled: [1, Transfer Complete interrupt enabled]
+  EN:
+    Disabled: [0, Channel disabled]
+    Enabled: [1, Channel enabled]
diff --git a/devices/fields/dma/dma_wl.yaml b/devices/fields/dma/dma_wl.yaml
@@ -1,75 +1,10 @@
-ISR:
-  TCIF?:
-    NotComplete: [0, No transfer complete event on channel x]
-    Complete: [1, A transfer complete event occurred on channel x]
-  HTIF?:
-    NotHalf: [0, No half transfer event on channel x]
-    Half: [1, A half transfer event occurred on channel x]
-  TEIF?:
-    NoError: [0, No transfer error on channel x]
-    Error: [1, A transfer error occurred on channel x]
-  GIF?:
-    NoEvent: [0, "No TE, HT or TC event on channel x"]
-    Event: [1, "A TE, HT or TC event occurred on channel x"]
-IFCR:
-  TCIF?:
-    Clear: [1, Clear the corresponding TCIFx flag]
-  HTIF?:
-    Clear: [1, Clear the corresponding HTIFx flag]
-  TEIF?:
-    Clear: [1, Clear the corresponding TEIFx flag]
-  GIF?:
-    Clear: [1, Clear the corresponding CGIFx flag]
+_include:
+  - common.yaml
+
 CCR?:
   PRIV:
     Disabled: [0, Disabled]
     Enabled: [1, Enabled]
-  MEM2MEM:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
-  PL:
-    Low: [0, Low]
-    Medium: [1, Medium]
-    High: [2, High]
-    VeryHigh: [3, Very high]
-  MSIZE:
-    Bits8: [0, 8 bits]
-    Bits16: [1, 16 bits]
-    Bits32: [2, 32 bits]
-  PSIZE:
-    Bits8: [0, 8 bits]
-    Bits16: [1, 16 bits]
-    Bits32: [2, 32 bits]
-  MINC:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
-  PINC:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
-  CIRC:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
-  DIR:
-    Peripheral: [0, Read from peripheral]
-    Memory: [1, Read from memory]
-  TEIE:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
-  HTIE:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
-  TCIE:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
-  EN:
-    Disabled: [0, Disabled]
-    Enabled: [1, Enabled]
 
 CNDTR?:
   NDT: [0, 0x3FFFF]
-
-CPAR?:
-  PA: [0, 0xFFFFFFFF]
-
-CMAR?:
-  MA: [0, 0xFFFFFFFF]
diff --git a/devices/fields/dma/dmamux_v1.yaml b/devices/fields/dma/dmamux_v1.yaml
@@ -14,7 +14,7 @@ C*CR:
   SOIE:
     Disabled: [0, Synchronization overrun interrupt disabled]
     Enabled: [1, Synchronization overrun interrupt enabled]
-RG*CR:
+RG?CR:
   GNBREQ: [0, 31]
   GPOL:
     NoEdge: [0, "No event, i.e. no detection nor generation"]
@@ -27,3 +27,28 @@ RG*CR:
   OIE:
     Disabled: [0, Trigger overrun interrupt disabled]
     Enabled: [1, Trigger overrun interrupt enabled]
+CSR:
+  SOF*:
+    NoSyncEvent:
+      [
+        0,
+        "No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
+      ]
+    SyncEvent:
+      [
+        1,
+        "Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
+      ]
+"CFR,CCFR":
+  CSOF*:
+    _W1C:
+      Clear: [1, Clear synchronization flag]
+RGSR:
+  "OF?":
+    NoTrigger:
+      [0, "No new trigger event occured on DMA request generator channel x, before the request counter underrun"]
+    Trigger: [1, "New trigger event occured on DMA request generator channel x, before the request counter underrun"]
+RGCFR:
+  COF?:
+    _W1C:
+      Clear: [1, Clear overrun flag]
diff --git a/devices/fields/dma/dmamux_wl.yaml b/devices/fields/dma/dmamux_wl.yaml
@@ -21,21 +21,6 @@ C?CR:
     lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"]
     lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"]
     lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"]
-  NBREQ: [0, 31]
-  SPOL:
-    NoEdge: [0, "No event, i.e. no synchronization nor detection"]
-    RisingEdge: [1, Rising edge]
-    FallingEdge: [2, Falling edge]
-    BothEdges: [3, Rising and falling edges]
-  SE:
-    Disabled: [0, Synchronization disabled]
-    Enabled: [1, Synchronization enabled]
-  EGE:
-    Disabled: [0, Event generation disabled]
-    Enabled: [1, Event generation enabled]
-  SOIE:
-    Disabled: [0, Synchronization overrun interrupt disabled]
-    Enabled: [1, Synchronization overrun interrupt enabled]
   DMAREQ_ID:
     none: [0, No signal selected as request input]
     dmamux1_req_gen0: [1, "Signal `dmamux1_req_gen0` selected as request input"]
@@ -81,18 +66,6 @@ C?CR:
     subghzspi_rx: [41, "Signal `subghzspi_rx` selected as request input"]
     subghzspi_tx: [42, "Signal `subghzspi_tx` selected as request input"]
 RG?CR:
-  GNBREQ: [0, 31]
-  GPOL:
-    NoEdge: [0, "No event, i.e. no detection nor generation"]
-    RisingEdge: [1, Rising edge]
-    FallingEdge: [2, Falling edge]
-    BothEdges: [3, Rising and falling edges]
-  GE:
-    Disabled: [0, DMA request generation disabled]
-    Enabled: [1, DMA request enabled]
-  OIE:
-    Disabled: [0, Trigger overrun interrupt disabled]
-    Enabled: [1, Trigger overrun interrupt enabled]
   SIG_ID:
     exti0: [0, "Signal `EXTIx` selected as synchronization input"]
     exti1: [1, "Signal `EXTIx` selected as synchronization input"]
@@ -115,26 +88,3 @@ RG?CR:
     lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"]
     lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"]
     lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"]
-CSR:
-  SOF*:
-    NoSyncEvent:
-      [
-        0,
-        "No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
-      ]
-    SyncEvent:
-      [
-        1,
-        "Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ",
-      ]
-"CFR,CCFR":
-  CSOF*:
-    Clear: [1, Clear synchronization flag]
-RGSR:
-  "OF[0123]":
-    NoTrigger:
-      [0, "No new trigger event occured on DMA request generator channel x, before the request counter underrun"]
-    Trigger: [1, "New trigger event occured on DMA request generator channel x, before the request counter underrun"]
-RGCFR:
-  "COF[0123]":
-    Clear: [1, Clear overrun flag]
diff --git a/devices/fields/dma/v1.yaml b/devices/fields/dma/v1.yaml
@@ -1,58 +1,5 @@
-ISR:
-  TEIF*:
-    NoError: [0, No transfer error]
-    Error: [1, A transfer error has occured]
-  HTIF*:
-    NotHalf: [0, No half transfer event]
-    Half: [1, A half transfer event has occured]
-  TCIF*:
-    NotComplete: [0, No transfer complete event]
-    Complete: [1, A transfer complete event has occured]
-  GIF*:
-    NoEvent: [0, "No transfer error, half event, complete event"]
-    Event: [1, "A transfer error, half event or complete event has occured"]
-IFCR:
-  CTEIF*:
-    Clear: [1, Clears the TEIF flag in the ISR register]
-  CHTIF*:
-    Clear: [1, Clears the HTIF flag in the ISR register]
-  CTCIF*:
-    Clear: [1, Clears the TCIF flag in the ISR register]
-  CGIF*:
-    Clear: [1, "Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register"]
-CCR*:
-  MEM2MEM:
-    Disabled: [0, Memory to memory mode disabled]
-    Enabled: [1, Memory to memory mode enabled]
-  PL:
-    Low: [0, Low priority]
-    Medium: [1, Medium priority]
-    High: [2, High priority]
-    VeryHigh: [3, Very high priority]
-  "[MP]SIZE":
-    Bits8: [0, 8-bit size] # or Byte
-    Bits16: [1, 16-bit size] # or HalfWord
-    Bits32: [2, 32-bit size] # or Word
-  "[MP]INC":
-    Disabled: [0, Increment mode disabled]
-    Enabled: [1, Increment mode enabled]
-  CIRC:
-    Disabled: [0, Circular buffer disabled]
-    Enabled: [1, Circular buffer enabled]
-  DIR:
-    FromPeripheral: [0, Read from peripheral]
-    FromMemory: [1, Read from memory]
-  TEIE:
-    Disabled: [0, Transfer Error interrupt disabled]
-    Enabled: [1, Transfer Error interrupt enabled]
-  HTIE:
-    Disabled: [0, Half Transfer interrupt disabled]
-    Enabled: [1, Half Transfer interrupt enabled]
-  TCIE:
-    Disabled: [0, Transfer Complete interrupt disabled]
-    Enabled: [1, Transfer Complete interrupt enabled]
-  EN:
-    Disabled: [0, Channel disabled]
-    Enabled: [1, Channel enabled]
+_include:
+  - common.yaml
+
 CNDTR*:
-  NDT: [0, 65535]
+  NDT: [0, 0xFFFF]
diff --git a/devices/patches/dma/dmamux_add_csr06.yaml b/devices/patches/dma/dmamux_add_csr06.yaml
@@ -0,0 +1,29 @@
+_add:
+  CSR:
+    displayName: CSR
+    description: DMAMUX request line multiplexer interrupt channel status register
+    addressOffset: 128
+    size: 32
+    access: read-only
+    resetValue: 0
+    resetMask: 4294967295
+    fields:
+      SOF:
+        description: Synchronization Overrun Flag
+        bitOffset: 0
+        bitWidth: 7
+        access: read-only
+  CFR:
+    displayName: CFR
+    description: DMAMUX request line multiplexer interrupt clear flag register
+    addressOffset: 132
+    size: 32
+    access: write-only
+    resetValue: 0
+    resetMask: 4294967295
+    fields:
+      CSOF:
+        description: Synchronization Clear Overrun Flag
+        bitOffset: 0
+        bitWidth: 7
+        access: write-only
diff --git a/devices/patches/dma/dmamux_split.yaml b/devices/patches/dma/dmamux_split.yaml
@@ -0,0 +1,8 @@
+CFR:
+  _split: CSOF
+RGSR:
+  _split: OF
+RGCFR:
+  _split: COF
+CSR:
+  _split: SOF
diff --git a/devices/patches/dma/h7_dmamux.yaml b/devices/patches/dma/h7_dmamux.yaml