A 14T SRAM bit-cell, implemented in 130-nm CMOS technology, with excellent read stability and soft error tolerance performance has been proposed. The parasitic extracted simulations show that compared with considered memory cells, the proposed cell achieves up to 146% read access time saving at the cost of acceptable layout area and leakage power dissipation overhead. The RSNM of 14T bit-cell is about x2.6 that of DICE structure, revealing excellent read stability. In addition, the proposed cell provides larger the critical charge, which indicates more superior soft error resilience ability.

To achieve reduction in test time of accelerators, broadcasting of test patterns is used for simultaneous testing of processing elements (PEs). However, number of PEs tested simultaneously is limited because of scan shift power constraint. In this letter, a Master-Slave based test pattern application method is proposed that alleviates this scan shift power constraint. PEs are grouped in Subcores, the tester loads the pattern into Master PE of Subcores. From Master, test patterns are loaded into adjacent Slave PEs of Subcore. By limiting scan shift power to one Master PE per Subcore, more PEs are allowed to be tested simultaneously.

Radio detection and ranging (RADAR) always suffers from clutters, which extremely constrains its maximum operation distance. To mitigate such intrinsic and common problem, a novel polarization-converse tag on targets is proposed and designed with an integration of a shared-aperture dual-linearly-polarized (DLP) antenna, a microstrip hybrid coupler, and two RF grounded (GND) stubs, which can directly transform polarizations of transmitting interrogation (e.g., vertical polarization) to converse-polarization backscatters (e.g., horizontal polarization) insulated from clutters. The proposed polarization-converse tag design is validated by the theoretical analysis as well as experimental results, which brings a prospect for RADAR applications.

Next generation satellite communications (NGSC) evolved by 5G NR combination is the hot issue in recent researches. For the conditions of new frequency (Ku/Ka/Q/V) and much more broadband (>100MHz) for satellite mobile communications, the obvious nonlinearity by Input Multiplexing (IMUX) filter, High Power Amplifier (HPA), and Output Multiplexing (OMUX) filter will cause serious signals degradation. Traditional behavioral modeling methods of IMUX filter, HPA, and OMUX filter (IHO) are relatively independent of each other, which is difficult to quantitatively evaluate intrinsic modeling errors and cumulative modeling errors. That makes modeling errors of IHO cannot be compensated accurately. In this paper, we are the first to exploit a quantitative evaluation of cascade modeling errors for IHO. A novel accurate and low-complexity behavior model for IHO of LEO satellite based on the iterative compensation of cascade modeling errors (ICCE-IHO) is proposed. Based on the normalized least mean square (NLMS) algorithm, the ICCE-IHO model realizes accurate modeling and low-complexity. Experimental results show that the ICCE-IHO model can achieve a maximum 0.67dB improvement in Normalized Mean Square Error (NMSE), a maximum 2.24dB improvement in Adjacent Channel Error Power Ratio (ACEPR), and the hardware resource consumption is reduced by 28%.

Logic BIST is a safety mechanism, which performs testing for Automotive electronics. However, pseudorandom LBIST patterns results in increased test time and test power. In this letter, a novel time multiplexed LBIST is presented to overcome test related problems of AI accelerators. First, the accelerator array is divided into smaller sub arrays, which are tested on time multiplexed clock cycles. This: 1) improves overall test time, under the given test power limit, 2) allows reduction in shift power, under given test time limits and 3) since only one sub array is clocked at a time, the peak power is reduced.

An integrated permanent magnet (PM) brushless motor driver with commutation current ripple reduction strategy is proposed in this study. The speed control and commutation current ripple reduction can both be achieved by only adjusting the duty ratio of the main switch. The other six active switches controlled by low-frequency commutation signals determined from the Hall effect sensors. The operation principles of the driver in normal conduction period and commutation period are both analyzed. To reduce the commutation ripple current, a compensation strategy is also provided by modifying the main switch duty ratio. A 500W prototype of proposed driver for a PM brushless motor with a rated speed of 3000rpm was constructed to verify the performance and validity. From the experimental results under different load and speed conditions, it can be seen that the current ripple in the commutation period can be greatly reduced up to about 50%.

Convolutional neural networks (CNNs) have proven to be promising in various applications such as audio recognition, image classification, and video understanding. Winograd algorithm helps to reduce the complexity of computation in a convolution but suffers from poor compatibility for different convolution shapes. This work introduces a dynamic dimension-level fusion architecture based on Winograd for accelerating different dimensions of CNNs. We explore this Winograd architecture by designing Dimension Fusion, a dimension-level processing engine that dynamically fuses to match the convolution shape of individual CNN layers. The proposed architecture is the first work based on Winograd algorithm to be compatible with all convolution shapes (dimension, stride, and filter-size) and achieves highest PE efficiency up to 1.55x and energy efficiency up to 3.3x compared with the state-of-art accelerators.