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NOMBRE: Fabián Steven Garay Rairán CODIGO: 20101005114 Primer Corte Tarea

This document contains VHDL code for an improved ALU circuit. It describes an entity called alu with ports for two 4-bit inputs A and B, a 4-bit selection signal S, a mode signal M, a carry in signal Ci, a 4-bit output F, an equality output AeqB, and a carry out signal Co. The architecture contains signals to store intermediate values and a process to perform different operations on the inputs based on the selection and mode signals, assigning the results to the outputs.

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Fabian Steven Garay Rairan
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31 views3 pages

NOMBRE: Fabián Steven Garay Rairán CODIGO: 20101005114 Primer Corte Tarea

This document contains VHDL code for an improved ALU circuit. It describes an entity called alu with ports for two 4-bit inputs A and B, a 4-bit selection signal S, a mode signal M, a carry in signal Ci, a 4-bit output F, an equality output AeqB, and a carry out signal Co. The architecture contains signals to store intermediate values and a process to perform different operations on the inputs based on the selection and mode signals, assigning the results to the outputs.

Uploaded by

Fabian Steven Garay Rairan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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NOMBRE: Fabin Steven Garay Rairn

CODIGO: 20101005114
PRIMER CORTE
TAREA
Obtenga la descripcin VHDL para el circuito ALU mejorado
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity alu is
port (A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
S : in std_logic_vector (3 downto 0);
M : in std_logic;
Ci : in std_logic;
F : out std_logic_vector (3 downto 0);
AeqB : out std_logic;
Co : out std_logic);
end alu;
architecture Behavioral of alu
signal x : std_logic_vector (3
signal y : std_logic_vector (3
signal w : std_logic_vector (3
signal z : std_logic_vector (4

is
downto
downto
downto
downto

0);
0);
0);
0);

begin
process (S)
begin
if M='0' then
case (S) is
when "0000" =>
z<='0'&A;
when "0001" =>
z<='0'&A or B;
when "0010" =>
z<='0'&A or not B;
when "0011" =>
z<="11111";
when "0100" =>
x<=A;
y<=A and not B;
z<=x(3)&x+y;

when "0101" =>


x<=A or B;
y<=A and not B;
z<=x(3)&x+y;
when "0110" =>
z<=A(3)&A-B+"1111";
when "0111" =>
x<=A and B;
z<=x(3)&x+"1111";
when "1000" =>
x<=A and B;
z<=A(3)&A+x;
when "1001" =>
z<=A(3)&A+B;
when "1010" =>
x<=A or not B;
y<=A and B;
z<=x(3)&x+y;
when "1011" =>
x<=A and B;
z<=x(3)&x+"1111";
when "1100" =>
z<=A&'0';
when "1101" =>
x<=A or B;
z<=x(3)&x+A;
when "1110" =>
x<=A or not B;
z<=x(3)&x+A;
when "1111" =>
z<=A(3)&A+"1111";
when others =>
z<="00000";
end case;
w<=z(3 downto 0);
Co<=z(4);
else
case (S) is
when "0000" =>
w<=not A;
when "0001" =>
w<=not A and not B;
when "0010" =>
w<=not A and B;
when "0011" =>
w<="0000";
when "0100" =>
w<=not A or not B;
when "0101" =>
w<=not B;

when "0110" =>


w<=A xor B;
when "0111" =>
w<=A and not B;
when "1000" =>
w<= not A or B;
when "1001" =>
w<=A xnor B;
when "1010" =>
w<=B;
when "1011" =>
w<=A and B;
when "1100" =>
w<="1111";
when "1101" =>
w<=A or not B;
when "1110" =>
w<=A or B;
when "1111" =>
w<=A;
when others =>
w<="0000";
end case;
end if;
F<=w;
end process;
end Behavioral;

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