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Analog Integrated Circuits Lab

This document describes an analog integrated circuits lab experiment to plot the VI characteristics of an NMOS transistor. It includes DC analysis equations for drain current in different regions and the small signal model. It also outlines the procedures to obtain graphs for key transistor parameters like Rin, Rout, Gm vs Veff, Gm vs ID with constant W/L, and Gm vs width using Cadence simulations. The conclusion states that the simulated plots match well with the theoretical plots from textbooks.

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ruchi0690
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169 views10 pages

Analog Integrated Circuits Lab

This document describes an analog integrated circuits lab experiment to plot the VI characteristics of an NMOS transistor. It includes DC analysis equations for drain current in different regions and the small signal model. It also outlines the procedures to obtain graphs for key transistor parameters like Rin, Rout, Gm vs Veff, Gm vs ID with constant W/L, and Gm vs width using Cadence simulations. The conclusion states that the simulated plots match well with the theoretical plots from textbooks.

Uploaded by

ruchi0690
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Analog Integrated Circuits Lab 1

1. Objective: To plot VI Characteristics of NMOS Transistor. 2. DC-AC Analysis


DC-Analysis Gate To source Valtage: = Drain to Source Voltage: = Drain Current (Saturation Region): = 0 (Cuttoff Region) = = =
2

( ) [( )

2 2

] (Triode Region,)

( ) ( )2 (Saturation Region) ( ) ( )2 (1 + ( ))(Considering Channel length Modulation)

Where =

AC-Analysis

Fig 1: Small Signal Model of N-MOS Transistor (Courtesy, Analog Integrated Circuit Design, 2nd Edition by Tony Chan Carusone, David A. Johns, Kenneth W. Martin)


Pg. 1

= =

2( +0 ) 1 2 0

= ( ) = ( )

Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

(A) NMOS Curves: Schematic:

To get the Curve, 1. Parameter To be varied, VDS 2. Sweep VGS 3. Plot of Current Obtained At Drain For Varying VDS Curve of ID Vs VDS, For Different VGS

Pg. 2
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

(B) Graph for Rin : Schematic:

To get the Curve, 1. Plot of Current at gate for small AC voltage at input with output(drain) grounded. 2. Rin = 1/Slope Response:

Pg. 3
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

(C) Graph for Rout : Schematic:

To get the Curve, 1. Plot of Current at gate for small AC voltage at output with input(Source) grounded 2. Rout = 1/Slope Response:

Pg. 4
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

(D) Gm VS Veff: Schematic:

To get the Curve, 1. Varying VGS using variable x, which eventually changes Veff . Here, Veff = VGS - Vth 2. = ( )

Pg. 5
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

Response:

Pg. 6
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

(E) Gm VS ID Keeping W/L Constant : Schematic:

Pg. 7
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

To get the Curve, 1. Varying ID, we get variation in gm 2. = ( ) Response:

Pg. 8
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

(F) Gm VS Width: Schematic:

To get the Curve, 1. Varying w by varying variable wd, we get variation in gm 2. = ( ) , Here ID and Veff is constant.

Pg. 9
Ruchi C. Gujarathi (1206486836)

Analog Integrated Circuits Lab 1

Response:

Conclusion: The graphs of Various DC and AC Parameters of N-MOS plotted in Cadence are nearly similar to theoretical plots given in the textbook.

Pg. 10
Ruchi C. Gujarathi (1206486836)

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