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Ec 2303iec 53 - Computer Architecture Organization: B.E.Fb - Tech. Degree Examination, Novemberjdecember 2012

1. The document discusses various topics related to computer architecture and organization including: 2. The von Neumann bottleneck, reducing adder delay, multiplication speedup techniques, branch prediction, asynchronous DRAMs, locality, traces, bus masters, instruction types, addressing modes, Booth's algorithm, floating point operations, pipeline hazards and remedies, superscalar processing, microprogrammed control units, virtual memory, random access memory, associative memory basics and construction. 3. The questions assess knowledge on these topics through definitions, explanations with examples, descriptions of algorithms, architectures and techniques.

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Somasundaram Ramu
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78 views2 pages

Ec 2303iec 53 - Computer Architecture Organization: B.E.Fb - Tech. Degree Examination, Novemberjdecember 2012

1. The document discusses various topics related to computer architecture and organization including: 2. The von Neumann bottleneck, reducing adder delay, multiplication speedup techniques, branch prediction, asynchronous DRAMs, locality, traces, bus masters, instruction types, addressing modes, Booth's algorithm, floating point operations, pipeline hazards and remedies, superscalar processing, microprogrammed control units, virtual memory, random access memory, associative memory basics and construction. 3. The questions assess knowledge on these topics through definitions, explanations with examples, descriptions of algorithms, architectures and techniques.

Uploaded by

Somasundaram Ramu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B.E.fB.Tech. DEGREE EXAMINATION, NOVEMBERJDECEMBER 2012.

Fifth Semester Electronics and Corumumcation Engineering EC 2303IEC 53 - COMPUTER ARCHITECTURE AND ORGANIZATION (Common to Sixth Semester Biomedical Engineering) (Regulation 2008) (Common to PTEC 2303 - Computer Architecture and Organization for RE. (part-Time) Fourth Semester, Electronics and Communication Engineering, Regulation 2009) Time: Three hours Answer ALL questions. PART A - (10
x

Maximum: 100 marks

20 marks)

1. 2. 3.
4.

What do you mean by von Neumann bottleneck? Specify the CPU performance equation. What are the two approaches to reduce the delay in adders? What are the two techniques to speed up the multiplication operation? What is the drawback of assigning one bit position to each control signal? What is called static branch prediction and dynamic branch prediction? Wha j are asynchronous DRAMs? What is temporal locality? What is trace? What is a bus master?

5.
6. 7.

8. 9. 10.

PART B

(5

16

80 marks)
(16)

11.

(a)

Explain the various Instruction types with examples. Or

(b) 12. (a)

Write in detail about various addressing modes. Explain the Booth's algorithm for multiplication of signed

(16) two's

compJement numbers using an example. Or (b) 13. (a) Explain the floating point addition and subtraction. (16)

Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to overcome/minimize these hazards? (8 + 8) Or

(b)

(i) (ii)

Describe the characteristics of super scalar processing. With a suitable diagram describe the basic structure of micro programmed control unit.

14.

(a)

(i) (ii)

Describe briefly about virtual memory . Write a note on Random access memories. Or

(8) (8)

(b)

Give the basic cell of an associative memory and explain its operation. Show how associative memorIes can be constructed using this basic cell with match logic. (16) (16)

15.

(a)

Describe the data transfer method using DMA Or

(b)

(i) (ii)

Explain different type's bus arbitration scheme. Describe vectored interrupt scheme with neat block diagram. (8 + 8)

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