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Verilog Module: Roll No.: (Full) : A05 Registration: 11109867 Name: PRINCE SHARMA

The document describes a Verilog module that implements all basic logic gates - AND, OR, NOT, NAND, NOR, XOR, and XNOR - in a single program. It defines the module with inputs a and b and outputs for each gate logic. A test bench is also provided to simulate the module by applying different combinations of inputs and observing the outputs.

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Prince Sharma
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53 views4 pages

Verilog Module: Roll No.: (Full) : A05 Registration: 11109867 Name: PRINCE SHARMA

The document describes a Verilog module that implements all basic logic gates - AND, OR, NOT, NAND, NOR, XOR, and XNOR - in a single program. It defines the module with inputs a and b and outputs for each gate logic. A test bench is also provided to simulate the module by applying different combinations of inputs and observing the outputs.

Uploaded by

Prince Sharma
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Roll No.

:( Full): a05

Registration: 11109867

Name: PRINCE SHARMA

Aim: Design all gates in one programme.

verilog module
module allgates(a,b,and1,or1,not1,not2,nand1,nor1,xor1,xnor1); input a,b; output and1,or1,not1,not2,nand1,nor1,xor1,xnor1; assign and1=a&b; assign or1=a|b; assign not1=~(a); assign not2=~(b); assign nand1=~(a&b); assign nor1=~(a|b); assign xor1=(a^b); assign xnor1=~(a^b); endmodule

text bench module allgatestb; // Inputs

reg a; reg b; // Outputs wire and1; wire or1; wire not1; wire not2; wire nand1; wire nor1; wire xor1; wire xnor1; // Instantiate the Unit Under Test (UUT) allgates uut ( .a(a), .b(b), .and1(and1), .or1(or1), .not1(not1), .not2(not2), .nand1(nand1), .nor1(nor1),

.xor1(xor1), .xnor1(xnor1) ); initial begin // Initialize Inputs a=0;b=0; #5 a=0;b=1; #5 a=1;b=0; #5 a=1;b=1; // Wait 100 ns for global reset to finish #5 $stop;

// Add stimulus here end endmodule

output

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