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Practical No - 1 Aim: Implementation of Gates.: 1) AND Gate

The document describes simulations of 7 basic logic gates: AND, OR, NOT, NOR, NAND, XOR, and XNOR. For each gate, it provides the Verilog program code that defines the gate module and its inputs/outputs, as well as a test bench module that instantiates the gate and applies test stimuli to its inputs in order to simulate and verify its output behavior.

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Prince Sharma
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67 views18 pages

Practical No - 1 Aim: Implementation of Gates.: 1) AND Gate

The document describes simulations of 7 basic logic gates: AND, OR, NOT, NOR, NAND, XOR, and XNOR. For each gate, it provides the Verilog program code that defines the gate module and its inputs/outputs, as well as a test bench module that instantiates the gate and applies test stimuli to its inputs in order to simulate and verify its output behavior.

Uploaded by

Prince Sharma
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Practical No - 1 Aim: Implementation of gates.

1) AND Gate
Program: module gateand(a, b, c); input a; input b; output c; assign c=a&b;

endmodule

Testbench: module gateandtb_v;

// Inputs reg a; reg b;

// Outputs wire c;

// Instantiate the Unit Under Test (UUT) gateand uut ( .a(a), .b(b), .c(c) );

initial begin // Initialize Inputs a = 0; b = 0;

// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop;

// Add stimulus here

end

endmodule

Simulation:

2) OR Gate
Program: module orgate(a, b, c); input a; input b; output c;

assign c=a|b; endmodule

Test bench: module orgatetb_v;

// Inputs reg a; reg b;

// Outputs wire c;

// Instantiate the Unit Under Test (UUT) orgate uut ( .a(a), .b(b), .c(c) );

initial begin // Initialize Inputs a = 0; b = 0;

// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=0;b=0;

#2 a=1;b=1; #2 $stop;

// Add stimulus here

end

endmodule

Simulation:

3) NOT Gate:

Program: module notgate(a, b); input a; output b;

assign b=~a; endmodule

Test bench: module notgatet_v;

// Inputs reg a;

// Outputs wire b;

// Instantiate the Unit Under Test (UUT) notgate uut ( .a(a), .b(b) );

initial begin // Initialize Inputs

a = 0;

// Wait 100 ns for global reset to finish #2 a=1; #2 $stop;

// Add stimulus here

end

endmodule

Simulation:

4) NOR gate:
Program: module norgate(a, b, c); input a; input b; output c;

assign c=~(a|b); endmodule

Test bench: module norgatetb_v;

// Inputs reg a; reg b;

// Outputs wire c;

// Instantiate the Unit Under Test (UUT) norgate uut ( .a(a), .b(b),

.c(c) );

initial begin // Initialize Inputs a = 0; b = 0;

// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop; // Add stimulus here

end

endmodule

Simulation:

5) NAND gate:
Program: module nandgate(a, b, c); input a; input b; output c; assign c=~(a&b);

endmodule

Test bench:

module nandgatetb_v;

// Inputs reg a; reg b;

// Outputs wire c;

// Instantiate the Unit Under Test (UUT) nandgate uut ( .a(a), .b(b), .c(c) );

initial begin // Initialize Inputs a = 0; b = 0;

// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1;

#2 $stop;

// Add stimulus here

end

endmodule

Simulation:

6) XOR gate:
Program:

module xorgate(a, b, c); input a; input b; output c; assign c=(a^b);

endmodule

Test Bench: module xorgatetb_v;

// Inputs reg a; reg b;

// Outputs wire c;

// Instantiate the Unit Under Test (UUT) xorgate uut ( .a(a), .b(b), .c(c) );

initial begin // Initialize Inputs a = 0; b = 0;

// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop;

// Add stimulus here

end

endmodule

Simulation:

7) XNOR gate:
Program: module xnorgate(a, b, c); input a; input b; output c; assign c=~(a^b);

endmodule

Test bench: module xnorgatetb_v;

// Inputs reg a; reg b;

// Outputs wire c;

// Instantiate the Unit Under Test (UUT) xnorgate uut ( .a(a), .b(b), .c(c) );

initial begin // Initialize Inputs a = 0; b = 0;

// Wait 100 ns for global reset to finish #2 a=0;b=1; #2 a=1;b=0; #2 a=1;b=1; #2 $stop;

// Add stimulus here

end

endmodule

Simulation:

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