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Verilog Quiz # 1

The document describes three ways to model a 2:1 multiplexer in Verilog: 1) Using gate-level modeling with OR, AND, and NOT gates. 2) Using continuous assignment statements to assign the output. 3) Using an "always" procedure block with an if-else statement to assign the output based on the select line value. The document is written in Chinese and English and appears to be a quiz asking to implement the 3 approaches to model a 2:1 multiplexer in Verilog.

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Chetan Gowda
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88 views2 pages

Verilog Quiz # 1

The document describes three ways to model a 2:1 multiplexer in Verilog: 1) Using gate-level modeling with OR, AND, and NOT gates. 2) Using continuous assignment statements to assign the output. 3) Using an "always" procedure block with an if-else statement to assign the output based on the select line value. The document is written in Chinese and English and appears to be a quiz asking to implement the 3 approaches to model a 2:1 multiplexer in Verilog.

Uploaded by

Chetan Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Verilog Quiz # 1

Use Verilog to describe the 2:1 multiplexer as shown in the following figure.

1. Use gate-level modeling.


module mux2_1 (SEL, A, B, OUT)

OR
(

input SEL, A, B;
) ;

output OUT ;
NOT (

endmodule

) ;

2. Use continuous assignment


statements.

AND

module mux2_1 (SEL, A, B, OUT)

(
) ;

input SEL, A, B;
output OUT ;

AND

assign Out

=
) ;

;
endmodule

3. Use an "always" procedure block.


module mux2_1 (SEL, A, B, OUT)
input SEL, A, B;
output OUT ;
reg OUT ;
always
@(
) begin
if (SEL)

;
else

;
end
endmodule

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