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Along With The Test Bench:-I) All Basic Gates Ii) Half Adder, Full Adder, Half Subtractor, Full Subtractor (Using Structural Modelling Style)

The document describes Verilog code and test benches for basic logic gates (AND, OR, NOT, NOR, XOR, XNOR) and combinational logic circuits (half adder, full adder, half subtractor) as part of an assignment. Code snippets are provided for the Verilog modules and test benches to test each logic gate and circuit, along with expected output waveforms.

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146 views12 pages

Along With The Test Bench:-I) All Basic Gates Ii) Half Adder, Full Adder, Half Subtractor, Full Subtractor (Using Structural Modelling Style)

The document describes Verilog code and test benches for basic logic gates (AND, OR, NOT, NOR, XOR, XNOR) and combinational logic circuits (half adder, full adder, half subtractor) as part of an assignment. Code snippets are provided for the Verilog modules and test benches to test each logic gate and circuit, along with expected output waveforms.

Uploaded by

Akshat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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19EC037 EC382

ASSIGNMENT : Design and Implement HDL code for following


along with the test bench :-
i)All basic gates ii) Half adder, Full adder, Half subtractor, Full
subtractor(using structural modelling style)
i) 1. AND Gate
VERILOG CODE :
module and_gate(a, b, c);
input a, b;
output c;
assign c= a & b;
endmodule
TESTBENCH :
module and_tb;
reg a,b;
wire c;
initial begin
a = 0; b = 0;
#1 a = 0; b = 1;
#1 a = 1; b = 0;
#1 a = 1; b = 1;
end
initial begin
$monitor ("%t | a = %d| b = %d| c = %d", $time, a, b, c);
$dumpfile("dumpand.vcd");
$dumpvars();
end
endmodule
19EC037 EC382

OUTPUT :

2. OR Gate
VERILOG CODE :
module or_gate(a,b,c);
input a,b;
output c;
assign c= a|b;
endmodule
TESTBENCH :
module or_tb;

reg a;
reg b;
wire c;
19EC037 EC382

or_gate uut (.a(a), .b(b), .c(c));


initial begin
a= 0; b = 0;
#100 a= 0; b=1;
#100 a=1;b=0;
#100 a=1; b=1;
end
initial begin
$monitor( " %t | a= %d; b= %d; | c = %d;" , $time, a,b,c);
$dumpfile ( "dumpor.vcd");
$dumpvars();
end
endmodule
OUTPUT :
19EC037 EC382

3.NOT Gate
VERILOG CODE :
module not_gate(a,y);
input a;
output y;
assign y = ~a;
endmodule
TESTBENCH :
module not_gate_tb;

reg a;
wire y;

not_gate uut (.a(a), .y(y));


initial begin
a= 0;
#10 a=1;
#10 a=0;
end
initial begin
$monitor( " %t | a= %d; | y= %d;" , $time, a,y);
$dumpfile ( "dumpnot.vcd");
$dumpvars();
end
endmodule
19EC037 EC382

OUTPUT :

4.NOR Gate
VERILOG CODE :
module nor_gate(a,b,c);
input a,b;
output c;
assign c = ~(a | b);
endmodule
TESTBENCH :
module nor_tb;

reg a;
reg b;
wire c;

nor_gate uut (.a(a), .b(b), .c(c));


19EC037 EC382

initial begin
a= 0; b = 0;
#100 a= 0; b=1;
#100 a=1;b=0;
#100 a=1; b=1;
end
initial begin
$monitor( " %t | a= %d; b= %d; | c = %d;" , $time, a,b,c);
$dumpfile ( "dumpnor.vcd");
$dumpvars();
end
endmodule
OUTPUT :
19EC037 EC382

5. XOR Gate
VERILOG CODE :
module xor_gate(a,b,c );
input a, b;
output c;
assign c = a^b;
endmodule
TESTBENCH :
module gate();
reg a,b;
wire y;
exor_gate uut (.a(a),.b(b),.y(y));
initial begin
#10 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
endmodule
OUTPUT :
19EC037 EC382

6. XNOR Gate
VERILOG CODE :
module xnor_gate(a,b,y);
input a,b;
output y;
xnor X1(y,a,b);
endmodule
TESTBENCH :
module gate();
reg a,b;
wire y;
xnor_gate uut (.a(a),.b(b),.y(y));
initial begin

#10 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
endmodule
OUTPUT :
19EC037 EC382

ii) HALF-ADDER
VERILOG CODE :
module half_adder(a,b,s,c);

input a,b;

output s,c;

xor X1(s,a,b);

and A1(c,a,b);

endmodule

TESTBENCH :
module testbench();

reg a,b;

wire s,c;

half_adder uut (.a(a), .b(b), .s(s), .c(c));

initial begin

#10 a=0;b=0;
19EC037 EC382

#10 a=0;b=1;

#10 a=1;b=0;

#10 a=1;b=1;

end

endmodule

OUTPUT :

HALF-SUBSTRACTOR

VERILOG CODE :
module half_sub(a,b,D,B);

input a,b;

output D,B;

wire x;

xor x1(D,a,b);

not N1(x,a);

and A1(B,x,b);

endmodule
19EC037 EC382

TESTBENCH :
module half_tb;

reg a;

reg b;

// Outputs

wire D;

wire B;

// Instantiate the Unit Under Test (UUT)

half_sub uut (

.a(a),

.b(b),

.D(D),

.B(B)

);

initial begin

// Initialize Inputs

#10 a = 0;b = 0;

#10 a = 0;b = 1;

#10 a = 1;b = 0;

#10 a = 1;b = 1;

end

endmodule
19EC037 EC382

OUTPUT :

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