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VHDL Code For A D Flip Flop

The document contains VHDL code for several digital logic components including D flip-flops with and without reset and clear, a JK flip-flop, 2-to-1 multiplexer, serial-to-parallel and parallel-to-serial converters, 4-bit counter, 1-bit adder, and finite state machine. The code defines the logic and state transitions for each component using if/else statements and case statements to assign values to outputs based on inputs and clock signals.

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3K views5 pages

VHDL Code For A D Flip Flop

The document contains VHDL code for several digital logic components including D flip-flops with and without reset and clear, a JK flip-flop, 2-to-1 multiplexer, serial-to-parallel and parallel-to-serial converters, 4-bit counter, 1-bit adder, and finite state machine. The code defines the logic and state transitions for each component using if/else statements and case statements to assign values to outputs based on inputs and clock signals.

Uploaded by

ashok_larkha4334
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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VHDL code for a D Flip Flop

process (signal names)


begin
if (clock’event and clock = ‘1’) then
output <= data;
end if;
end process

VHDL code for a D Flip Flop with Reset and Clear

if reset = ‘0’ then


output <= ‘0’;
elsif set = ‘0’ then
output <= ‘1’;
elsif (clock’event and clock = ‘1’) then
output <= data;
end if;

VHDL code for a D Flip Flop

if (clock’event and clock = ‘0’) then


if (reset = ‘0’ and data = ‘0’) then
output <= ‘0’;
elsif (reset = ‘0’ and data = ‘1’) then
output <= ‘0’;
elsif (reset = ‘1’ and data = ‘0’) then
output <= ‘0’;
elsif (reset = ‘1’ and data = ‘1’) then
output <= ‘1’;
end if;

VHDL code for a JK Flip Flop

if (clock’event and clock = ‘1’) then


if (in1 = ‘0’ and in2 = ‘0’) then
output <= output;
elsif (in1 = ‘1’ and in2 = ‘0’) then
output <= ‘1’;
elsif (in1 = ‘0’ and in2 = ‘1’) then
output <= ‘0’;
elsif (in1 = ‘1’ and in2 = ‘1’) then
output <= not(output);
end if;
end if;

VHDL code for a 2-to-1 Mux

if sel = ‘0’ then


output <= data1;
elsif sel = ‘1’ then
output <= data2;
end if;

VHDL code for a Serial to Parallel Converter


if clear = ‘0’ then
shift_reg <= “00000000”;
elsif (clock’event and clock = ‘1’) then
shift_reg(7 downto 1) <= (6 downto 0);
shift_reg(0) <= serial;
end if;

VHDL code for a Parallel to Serial Converter

if load = ‘0’ then


shift_reg <= parallel;
elsif (clock’event and clock = ‘1’) then
serial <= shift_reg(7);
shift_reg(7 downto 1) <= (6 downto 0);
end if;

VHDL code for a 4 bit Counter

if load = ‘0’ then


output <= “1111”;
elsif (clock’event and clock = ‘1’) then
output <= data - ‘1’;
end if;
carry <= ‘0’ when output = “0000” else ‘1’;
load <= carry;
VHDL code for a 1 bit Adder

if c = ‘0’ then
if (a and b) = ‘1’ then
sum <= ‘0’;
carry <= ‘1’;
elsif (a or b) = ‘1’ then
sum <= ‘1’;
carry <= ‘0’
end if;
elsif c = ‘1’ then
if (a and b) = ‘1’ then
sum <= ‘1’;
carry <= ‘1’;
elsif (a or b) = ‘1’ then
sum <= ‘0’;
carry <= ‘1’;
end if;
end if;

VHDL code for a State Machine

if reset = ‘0’ then


state <= stateA;
output <= ‘0’;
elsif (clock’event and clock) = ‘1’ then
case state is
when stateA
output <= ‘0’;
state <= stateB
when stateB
output <= ‘1’;
if input = ‘1’ then
state <= stateB;
else
state <=stateC;
end if;
when stateC
output <= ‘0’
state <= stateA;
end case;

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